Konica Minolta PCI-1712L user manual 4 Pre-Trigger Acquisition Mode

Chapter 5

Trigger Event

Acquired number of samples N 2 Samples

1	2	3	N	N+1	N+2
					t

Figure 5-4: Pre-Trigger Acquisition Mode

A/D Sample Clock Sources

The PCI-1712/1712L can adopt both internal and external clock sources for pacer, post-trigger, delay-trigger, about-trigger acquisition modes:

wInternal A/D sample clock with 16-bit Counter

wExternal A/D sample clock that is connected to AI_CLK on the PCLD-8712 screw terminal board.

The internal and external A/D sample clocks are described in more detail as follows.

qInternal A/D Sample Clock

The internal A/D sample clock uses a 10 MHz time base. Conversions start on the rising edge of the counter output. You can use software to specify the clock source as internal and the sampling frequency to pace the operation. The minimum frequency is 152.6 S/s, the maximum frequency is 2 MS/s. According to the sampling theory (Nyquist Theorem), you must specify a frequency that is at least twice as fast as the input’s highest frequency component to achieve a valid sampling. For example, to accurately sample a 20 kHz signal, you have to specify a sampling frequency of at least 40 kHz. This consideration can avoid an error condition often know as aliasing, in which high frequency input components appear erroneously as lower frequencies when sampling.

qExternal A/D Sample Clock

The external A/D sample clock is useful when you want to pace acquisitions at rates not available with the internal A/D sample clock, or when you want to pace at uneven intervals. Connect an external A/ D sample clock to screw terminal AI_CLK on the PCLD-8712 screw terminal board. Conversions will start on the rising edge of the external A/D sample clock input signal. You can use software to specify the clock source as external. The sampling frequency is always limited to a maximum of 2 MHz for the external A/D sample clock input signal.

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