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Konica Minolta PCI-1712L user manual D. Register Structure and Format, AppendixD, D.1 Overview

Models: PCI-1712L PCI-1712

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AppendixD

AppendixD

D. Register Structure and Format

D.1 Overview

The PCI-1712/1712L is delivered with an easy-to-use 32-bit DLL driver for user programming under Windows 95/98/NT operating system. We dvise users to program the PCI-1712/1712L using 32-bit DLL driver provided by Advantech to avoid the complexity of low-level program- ming by register.

The most important consideration in programming the PCI-1712/1712L at the register level is to understand the function of the card’s regis- ters. The information in the following sections is provided for users who would like to do their own register-level programming.

D.2 I/O Port Address Map

The PCI-1712/1712L requires 50 consecutive addresses in the PC’s I/O space. The address of each register is specified as an offset from the card’s base address. For example, BASE+0 is the card’s base address and BASE+8 is the base address plus eight bytes. The following sections give the detailed information about register layout, and also the detailed information about each register or driver and its address relative to the card’s base address.

Table D-1 shows the function of each register or driver and its address relative to the card’s base address.

Note

✎All base address is in hexadecimal in Appendix D.

✎Users have to use a 16-bit (word) I/O command to read/write each register.

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Konica Minolta PCI-1712L user manual D. Register Structure and Format, AppendixD, D.1 Overview, D.2 I/O Port Address Map

Contents

1 MS/s, 12-bit, 16-ch High- Speed Multifunction Card PCI-1712/1712L Users manualPCI-1712/1712L Quick Start Driver InstallationHardware Installation Verifying your InstallationDevice Installation Copyright 2nd EditionPrinted in Taiwan March1. Introduction Contents2. Installation 3. Signal ConnectionsAppendix C. Screw-terminal Board Appendix A. SpecificationAppendix B. Block Diagram 6. CalibrationD/A Channel Data for Continuous Output Operation Mode Digital I/O configuration registers - Write/Read BASE+2ADigital I/O registers - Write/Read BASE+28 Figures Figure 6-14 Adjusting registers Figure 6-5 A/D Calibration ProcedureFigure 6-6 A/D Calibration Procedure Figure 6-7 A/D Calibration ProcedureTables Table D-23 Calibration command Table D-20 Register for digital I/O configurationTable D-21 Register for digital I/O configuration Table D-22 Register for calibration commandPage PCI-1712 1 MS/s High-Speed Multifunction Card 1.1 Features1. Introduction Chapter1Chapter q PCI-1712/1712L DAS card q PCI-1712/1712L User’s Manual 1.2 Installation Guideq Wiring cable q Wiring boardChapter Figure 1-1 Installation Flow ChartPCI-1712/1712L User’s Manual Wiring Cable 1.3 AccessoriesWiring Boards PCI-1712/1712L User’s Manual ChapterChapter2 2. Installation2.1 Unpacking Figure 2-1 The Setup Screen of Advantech Automation Software 2.2 Driver InstallationFigure 2-2 Different options for Driver Setup 2.3 Hardware InstallationStep 2 Remove the cover of your computer Figure 2-3 The device name listed on the Device Manager Setting Up the Device 2.4 Device Setup & ConfigurationFigure 2-4 The Advantech Device Installation utility program Figure 2-5 The I/O Device Installation dialog boxFigure 2-6 The “Devices Found” dialog box Figure 2-7 The Device Setting dialog boxConfiguring the Device for unipolar By inputting an external reference voltage xV, where 0=x=10you will get a output voltage range 0 toFigure 2-9 Analog Input tab on the Device Test dialog box 2.5 Device TestingTesting Analog Input Function Testing Digital Input Function Figure 2-10 Analog Input tab on the Device Test dialog boxFigure 2-11 Analog Output tab on the Device Test dialog box Testing Analog Output Function PCI-1712 onlyTesting Counter Function Figure 2-12 Digital Input tab on the Device Test dialog boxFigure 2-13 Digital Output tab on the Device Test dialog box Testing Digital Output Functionconfigure the Pulse Frequency by the scroll bar right below it Figure 2-14 Digital output tab on the Device Test dialog boxChapter3 3. Signal Connections3.2 I/O Connector 3.1 OverviewPins 20, 22~25, 54, 56~59 are not defined on PCI-1712L Figure 3-1 I/O connector pin assignments for the PCI-1712/1712LPCI-1712/1712L User’s Manual Description Table 3-1 I/O Connector Signal Description PartSignal Name DirectionDirection Table 3-1 I/O Connector Signal Description PartSignal Name ReferenceDescription Table 3-1 I/O Connector Signal Description PartSignal Name DirectionDifferential Channel Connections 3.3 Analog Input ConnectionsFigure 3-2 Single-ended input channel connection Single-ended Channel ConnectionsFigure 3-3 Differential input channel connection - ground reference signal sourcesource Figure 3-4 Differential input channel connection - floating signalFigure 3-5 Analog output connections 3.4 Analog Output Connections3.5 Field Wiring Considerations Chapter4 4. Software Overview4.1 Programming Choices q Visual C++ q Visual Basic q Delphi q C++ Builder 4.2 DLL Driver Programming Roadmapq Port Function Group q Communication Function Group q Temperature Measurement Function Group q Alarm Function Groupq Analog Iutput Function Group q Analog Output Function Group q Digital Input/Output Function Group q Counter Function GroupPCI-1712/1712L User’s Manual ChapterTable 5-1 Gains and Analog Input Range 5.1 Analog Input Features5. Principles of Operation Chapter5q Single Value Acquisition Mode Figure 5-2 Delay-Trigger Acquisition Mode Figure 5-1 Post-Trigger Acquisition ModeFigure 5-3 About-Trigger Acquisition Mode w Internal A/D sample clock with 16-bit Counter Figure 5-4 Pre-Trigger Acquisition Modew Software trigger w External digital TTL trigger, and Figure 5-5 PCI-1712/1712L Sample Clock Sourceq Analog Threshold Trigger Table 5-2 Analog Input Data FormatTable 5-3 The corresponding Full Scale values for various Input Voltage Ranges5.2 Analog Output Features channel Chapter Analog Output Data Format 5.3 Digital I/O FeaturesTable 5-4 Analog Output Data Format Table 5-5 The corresponding Full Scale values for various Output5.4 Counter/Timer Features q Logic-low external gate input q Event counting Chapter Chapter Chapter Figure 5-6 Frequency measurementdh= inportaddr21712+0x1c8 Chapterdl= inportaddr21712+0x1c Read low byteChapter 65535-50000/1K = 15.535 sec Figure 5-7 Pulse width measurementCNT2’s gate input is low ChapterShow the duty ratio of positive ChapterFigure 6-1 PCI-1712/1712L VR1 & TP5 6. CalibrationChapter6 6.1 VR Assignment6.2 A/D Calibration 6.3 D/A Calibration Figure 6-2 Selecting the device you want to calibrate 6.4 Calibration UtilityFigure 6-4 Auto A/D Calibration Dialog Box Figure 6-3 Warning message before start calibrationA/D channel Auto-Calibration Step 6 The second A/D calibration procedure is enabled Fig Figure 6-5 A/D Calibration ProcedureFigure 6-6 A/D Calibration Procedure Step 5 The first A/D calibration procedure is enabled FigStep 8 Auto-calibration is finished. See fig Figure 6-7 A/D Calibration ProcedureFigure 6-8 A/D Calibration is finished Step 7 The third A/D calibration procedure is enabled FigFigure 6-10 Calibrating D/A Channel Figure 6-9 Range Selection in D/A CalibrationStep 10 D/A channel 0 calibration is enabled Fig Step 12 Auto-calibration is finished Fig Figure 6-11 Calibrating D/A ChannelFigure 6-12 D/A Calibration is finished Step 11 D/A channel 1 calibration is enabled FigA/D channel Manual-Calibration Figure 6-13 Selecting Input Rage in Manual A/D Calibration panelFigure 6-14 Adjusting registers Choosing Output Voltage Figure 6-15 & Figure 6-16 Selecting D/A Range andD/A channel Manual-Calibration Figure 6-17 Adjusting registers PCI-1712/1712L User’s Manual ChapterAppendix A A. SpecificationPCI-1712 User’s Manual PCI-1712/1712L User’s Manual APPENDIX AAnalog Output PCI-1712 only Digital Input /OutputGeneral Counter/TimerPCI-1712/1712L User’s Manual APPENDIX AA I T R G A O T R G B. Block DiagramAppendix B PCI BUSPCI-1712/1712L User’s Manual APPENDIX BAppendixC C. 2 FeaturesC. Screw-terminal Board C. 1 IntroductionPCI-1712/1712L User’s Manual C.4 Pin AssignmentFigure C-2 CN2 pin assignments for the PCLD-8712 APPENDIX CC.5 Single-ended Connections f3dB = 2π RAn+RAn+1 CDn C.6 Differential ConnectionsRDn RAn+RAn+1+RDn D.2 I/O Port Address Map D. Register Structure and FormatAppendixD D.1 OverviewAPPENDIX D Table D-1 PCI-1712/1712L register format PartPCI-1712/1712L User’s Manual Table D-1 PCI-1712/1712L register format Part APPENDIX DTable D-1 PCI-1712/1712L register format Part APPENDIX DPCI-1712/1712L User’s Manual D.4 Channel and A/D data - Read BASE + D.3 A/D Single Value Acquisition - Write BASE+0Table D-2 Register for channel number and A/D data Table D-3 Register for A/D channel range setting D.5 A/D Channel Range Setting - Write BASE+2STR3 ~ STR0 D.6 MUX Control - Write BASE+4Table D-4 Gain Codes for the PCI-1712/1712L Table D-5 Register for multiplexer controlAPPENDIX D Analog input acquisition mode register D.7 A/D Control/Status RegisterWrite/Read BASE+6 Table D-6 Register for A/D control/statusThis bit is used to select the A/D sample clock source Table D-7 Analog Input Acquisition ModeTable D-8 Register for clear interrupt and FIFO D.8 Clear interrupt and FIFO - Write BASE+8Clear interrupt Table D-9 Register for interrupt and FIFO status D. 9 Interrupt and FIFO status - Read BASE+8Table D-10 Register for D/A control D.10 D/A control/status register - Write/Read BASE+ADACLK Table D-11 Analog output operation modeDA1U/B D/A channel 1 unipolar or bipolar outputTable D-12 Register for D/A channel 0/1 data D.11 D/A Channel 0/1 Data - Write BASE+C/ETable D-13 Register for 82C54 counter chip D.12 82C54 Counter Chip 0 - Write/Read BASE+10 toTable D-14 Register for 82C54 counter chip D.13 82C54 counter chip 1 - Write/Read BASE+18 to 1ECn1 Cn0 = 1, 0, External clock is on connector CNTnCLK n = 0, 1 D.14 Counter gate and clock control/status - Write/ Read BASE+20 toTable D-15 Register for counter gate and clock control/status Table D-16 Table of Cn1 to Cn0 registerGn1 to Gn0 Counter gate source control register n = 0,1,2 Table D-17 Table of Gn1 to Gn0 registerCounter clock edge control register n = 0,1,2 Counter clock set register n = 0,1,2Counter gate polarity control register n = 0,1,2 Table D-18 Table for CLKSEL1 to CLKSEL0 register D.15 Digital I/O registers - Write/Read BASE+28Table D-19 Register for Digital I/O Table D-22 Register for calibration command D.16 Digital I/O configuration registers - Write/Read BASE+2AD.17 Calibration command registers - Write BASE+2C Table D-20 Register for digital I/O configurationCalibration data Table D-23 Calibration commandCM3 to CM0 Calibration command D7 to D0DA11 TO DA0 D/A data Table D-24 Register for D/A channel data