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Konica Minolta PCI-1712L user manual Principles of Operation, Analog Input Features

Models: PCI-1712L PCI-1712

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5. Principles of Operation

5. Principles of Operation

Chapter5

This chapter describes the analog input, analog output, digital I/O and counter/timer features of the PCI-1712/1712L card.

5.1 Analog Input Features

This section describes the following features of the analog input (A/D) of PCI-1712/1712L card:

wAnalog input ranges and gains

wAnalog input acquisition modes

wA/D sample clock sources

wTrigger sources

wAnalog Input Data Format

Analog Input Ranges and Gains

Each channel on the PCI-1712/1712L can measure unipolar and bipolar analog input signals. A unipolar signal can range between 0 to 10 V FSR, while a bipolar signal extends within ± 10 V FSR.

The PCI-1712/1712L is able to set different input ranges for each channel. When the channels are set as unipolar or bipolar input in FSR, the sampling rate can be up to 600 kS/s, but when there is a mixed combination of unipolar and bipolar inputs, it can operate only with a rate up to 400 kS/s.

The PCI-1712/1712L also provides various gain levels that are program- mable per channel. Table 5-1 lists the effective ranges supported by the PCI-1712/1712L using these gains.

Table 5-1: Gains and Analog Input Range

Gain	Unipolar Analog Input Range	Bipolar Analog Input Range

0.5	N/A	± 10 V

1	0 ~ 10 V	± 5V

2	0 ~ 5 V	± 2.5 V

4	0 ~ 2.5 V	± 1.25 V

8	0 ~ 1.25 V	± 0.625 V

For each channel, choose the gain level that provides most optimal range that can accommodate the signal range you have to measure. For detailed information, please refer to Appendix D.5 A/D Channel Range Setting.

Advantech Co., Ltd.	– 33 –	PCI-1712/1712L User’s Manual
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Konica Minolta PCI-1712L user manual Principles of Operation, Analog Input Features, 1 Gains and Analog Input Range

Contents

1 MS/s, 12-bit, 16-ch High- Speed Multifunction Card PCI-1712/1712L Users manualHardware Installation Driver InstallationVerifying your Installation PCI-1712/1712L Quick StartDevice Installation Printed in Taiwan 2nd EditionMarch Copyright2. Installation Contents3. Signal Connections 1. IntroductionAppendix B. Block Diagram Appendix A. Specification6. Calibration Appendix C. Screw-terminal BoardDigital I/O configuration registers - Write/Read BASE+2A Digital I/O registers - Write/Read BASE+28D/A Channel Data for Continuous Output Operation Mode Figures Figure 6-6 A/D Calibration Procedure Figure 6-5 A/D Calibration ProcedureFigure 6-7 A/D Calibration Procedure Figure 6-14 Adjusting registersTables Table D-21 Register for digital I/O configuration Table D-20 Register for digital I/O configurationTable D-22 Register for calibration command Table D-23 Calibration commandPage 1. Introduction 1.1 FeaturesChapter1 PCI-1712 1 MS/s High-Speed Multifunction CardChapter q Wiring cable 1.2 Installation Guideq Wiring board q PCI-1712/1712L DAS card q PCI-1712/1712L User’s ManualFigure 1-1 Installation Flow Chart ChapterPCI-1712/1712L User’s Manual 1.3 Accessories Wiring CableWiring Boards PCI-1712/1712L User’s Manual Chapter2. Installation Chapter22.1 Unpacking Figure 2-1 The Setup Screen of Advantech Automation Software 2.2 Driver InstallationFigure 2-2 Different options for Driver Setup 2.3 Hardware InstallationStep 2 Remove the cover of your computer Figure 2-3 The device name listed on the Device Manager Figure 2-4 The Advantech Device Installation utility program 2.4 Device Setup & ConfigurationFigure 2-5 The I/O Device Installation dialog box Setting Up the DeviceFigure 2-7 The Device Setting dialog box Figure 2-6 The “Devices Found” dialog boxConfiguring the Device you will get a output voltage range By inputting an external reference voltage xV, where 0=x=100 to for unipolar2.5 Device Testing Figure 2-9 Analog Input tab on the Device Test dialog boxTesting Analog Input Function Figure 2-11 Analog Output tab on the Device Test dialog box Figure 2-10 Analog Input tab on the Device Test dialog boxTesting Analog Output Function PCI-1712 only Testing Digital Input FunctionFigure 2-13 Digital Output tab on the Device Test dialog box Figure 2-12 Digital Input tab on the Device Test dialog boxTesting Digital Output Function Testing Counter Functionconfigure the Pulse Frequency by the scroll bar right below it Figure 2-14 Digital output tab on the Device Test dialog box3.2 I/O Connector 3. Signal Connections3.1 Overview Chapter3Figure 3-1 I/O connector pin assignments for the PCI-1712/1712L Pins 20, 22~25, 54, 56~59 are not defined on PCI-1712LPCI-1712/1712L User’s Manual Signal Name Table 3-1 I/O Connector Signal Description PartDirection DescriptionSignal Name Table 3-1 I/O Connector Signal Description PartReference DirectionSignal Name Table 3-1 I/O Connector Signal Description PartDirection DescriptionFigure 3-2 Single-ended input channel connection 3.3 Analog Input ConnectionsSingle-ended Channel Connections Differential Channel ConnectionsFigure 3-3 Differential input channel connection - ground reference signal sourcesource Figure 3-4 Differential input channel connection - floating signalFigure 3-5 Analog output connections 3.4 Analog Output Connections3.5 Field Wiring Considerations 4. Software Overview Chapter44.1 Programming Choices q Visual C++ q Visual Basic q Delphi q C++ Builder 4.2 DLL Driver Programming Roadmapq Analog Iutput Function Group q Analog Output Function Group q Temperature Measurement Function Group q Alarm Function Groupq Digital Input/Output Function Group q Counter Function Group q Port Function Group q Communication Function GroupPCI-1712/1712L User’s Manual Chapter5. Principles of Operation 5.1 Analog Input FeaturesChapter5 Table 5-1 Gains and Analog Input Rangeq Single Value Acquisition Mode Figure 5-2 Delay-Trigger Acquisition Mode Figure 5-1 Post-Trigger Acquisition ModeFigure 5-3 About-Trigger Acquisition Mode w Internal A/D sample clock with 16-bit Counter Figure 5-4 Pre-Trigger Acquisition Modew Software trigger w External digital TTL trigger, and Figure 5-5 PCI-1712/1712L Sample Clock SourceTable 5-3 The corresponding Full Scale values for various Input Table 5-2 Analog Input Data FormatVoltage Ranges q Analog Threshold Trigger5.2 Analog Output Features channel Chapter Table 5-4 Analog Output Data Format 5.3 Digital I/O FeaturesTable 5-5 The corresponding Full Scale values for various Output Analog Output Data Format5.4 Counter/Timer Features q Logic-low external gate input q Event counting Chapter Chapter Chapter Figure 5-6 Frequency measurementdl= inportaddr21712+0x1c ChapterRead low byte dh= inportaddr21712+0x1c8Chapter 65535-50000/1K = 15.535 sec Figure 5-7 Pulse width measurementCNT2’s gate input is low ChapterShow the duty ratio of positive ChapterChapter6 6. Calibration6.1 VR Assignment Figure 6-1 PCI-1712/1712L VR1 & TP56.2 A/D Calibration 6.3 D/A Calibration Figure 6-2 Selecting the device you want to calibrate 6.4 Calibration UtilityFigure 6-3 Warning message before start calibration Figure 6-4 Auto A/D Calibration Dialog BoxA/D channel Auto-Calibration Figure 6-6 A/D Calibration Procedure Figure 6-5 A/D Calibration ProcedureStep 5 The first A/D calibration procedure is enabled Fig Step 6 The second A/D calibration procedure is enabled FigFigure 6-8 A/D Calibration is finished Figure 6-7 A/D Calibration ProcedureStep 7 The third A/D calibration procedure is enabled Fig Step 8 Auto-calibration is finished. See figFigure 6-9 Range Selection in D/A Calibration Figure 6-10 Calibrating D/A ChannelStep 10 D/A channel 0 calibration is enabled Fig Figure 6-12 D/A Calibration is finished Figure 6-11 Calibrating D/A ChannelStep 11 D/A channel 1 calibration is enabled Fig Step 12 Auto-calibration is finished FigA/D channel Manual-Calibration Figure 6-13 Selecting Input Rage in Manual A/D Calibration panelFigure 6-14 Adjusting registers Figure 6-15 & Figure 6-16 Selecting D/A Range and Choosing Output VoltageD/A channel Manual-Calibration Figure 6-17 Adjusting registers PCI-1712/1712L User’s Manual ChapterA. Specification Appendix APCI-1712 User’s Manual Analog Output PCI-1712 only APPENDIX ADigital Input /Output PCI-1712/1712L User’s ManualGeneral Counter/TimerPCI-1712/1712L User’s Manual APPENDIX AAppendix B B. Block DiagramPCI BUS A I T R G A O T R GPCI-1712/1712L User’s Manual APPENDIX BC. Screw-terminal Board C. 2 FeaturesC. 1 Introduction AppendixCFigure C-2 CN2 pin assignments for the PCLD-8712 C.4 Pin AssignmentAPPENDIX C PCI-1712/1712L User’s ManualC.5 Single-ended Connections C.6 Differential Connections f3dB = 2π RAn+RAn+1 CDnRDn RAn+RAn+1+RDn AppendixD D. Register Structure and FormatD.1 Overview D.2 I/O Port Address MapTable D-1 PCI-1712/1712L register format Part APPENDIX DPCI-1712/1712L User’s Manual Table D-1 PCI-1712/1712L register format Part APPENDIX DAPPENDIX D Table D-1 PCI-1712/1712L register format PartPCI-1712/1712L User’s Manual D.3 A/D Single Value Acquisition - Write BASE+0 D.4 Channel and A/D data - Read BASE +Table D-2 Register for channel number and A/D data Table D-3 Register for A/D channel range setting D.5 A/D Channel Range Setting - Write BASE+2Table D-4 Gain Codes for the PCI-1712/1712L D.6 MUX Control - Write BASE+4Table D-5 Register for multiplexer control STR3 ~ STR0APPENDIX D Write/Read BASE+6 D.7 A/D Control/Status RegisterTable D-6 Register for A/D control/status ADM2 ~ ADM0This bit is used to select the A/D sample clock source Table D-7 Analog Input Acquisition ModeD.8 Clear interrupt and FIFO - Write BASE+8 Table D-8 Register for clear interrupt and FIFOClear interrupt Table D-9 Register for interrupt and FIFO status D. 9 Interrupt and FIFO status - Read BASE+8Table D-10 Register for D/A control D.10 D/A control/status register - Write/Read BASE+ADA1U/B Table D-11 Analog output operation modeD/A channel 1 unipolar or bipolar output DACLKTable D-12 Register for D/A channel 0/1 data D.11 D/A Channel 0/1 Data - Write BASE+C/ETable D-13 Register for 82C54 counter chip D.12 82C54 Counter Chip 0 - Write/Read BASE+10 toTable D-14 Register for 82C54 counter chip D.13 82C54 counter chip 1 - Write/Read BASE+18 to 1ETable D-15 Register for counter gate and clock control/status D.14 Counter gate and clock control/status - Write/ Read BASE+20 toTable D-16 Table of Cn1 to Cn0 register Cn1 Cn0 = 1, 0, External clock is on connector CNTnCLK n = 0, 1Counter clock edge control register n = 0,1,2 Table D-17 Table of Gn1 to Gn0 registerCounter clock set register n = 0,1,2 Gn1 to Gn0 Counter gate source control register n = 0,1,2Counter gate polarity control register n = 0,1,2 D.15 Digital I/O registers - Write/Read BASE+28 Table D-18 Table for CLKSEL1 to CLKSEL0 registerTable D-19 Register for Digital I/O D.17 Calibration command registers - Write BASE+2C D.16 Digital I/O configuration registers - Write/Read BASE+2ATable D-20 Register for digital I/O configuration Table D-22 Register for calibration commandCM3 to CM0 Calibration command Table D-23 Calibration commandD7 to D0 Calibration dataDA11 TO DA0 D/A data Table D-24 Register for D/A channel data