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Konica Minolta PCI-1712L user manual Appendix D

Models: PCI-1712L PCI-1712

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APPENDIX D

The write-only register of Write BASE+4 controls how the multiplexers (MUXs) scan.

wWrite BASE+4 bit 3 to bit 0, STR3 ~ STR0, hold the start scan channel number.

wWrite BASE+4 bit 11 to bit 8, STP3 ~ STP0, hold the stop scan channel number.

Writing to the register automatically initializes the MUXs to the start and stop channel. Each A/D conversion trigger also sets MUXs to the next channel. With continuous triggering, the MUXs will scan from the start channel to the stop channel and then repeat. The following examples show the scan sequences of the MUXs (all channels are set as single-ended).

Example 1

If the start scan input channel is AI3 and the stop scan input channel is AI7, then the scan sequence is AI3, AI 4, AI 5, AI6, AI7, AI3, AI4, AI5, AI6, AI7, AI3, AI4...

Example 2

If the start scan input channel is AI13 and the stop scan input channel is AI2, then the scan sequence is AI13, AI14, AI15, AI0, AI1, AI2, AI13, AI14, AI15, AI0, AI1, AI2, AI13, AI14...

The scan logic of PCI-1712/1712L card is pretty fancy and powerful, you can set gain code, B/U and S/D by each channel. The scan logic will be a little complex if you set the channel in differential mode. In differential mode, the even channel (i.e. AI0, AI2, AI4...AI14) and odd channel (i.e. AI1, AI3, AI5...AI15) are combined to one channel. The odd channel is the positive end and the even one is negative end. For example, if the AI0 is set as differential mode, then the AI0 and AI1 are combined to one channel and refer to the gain code and B/U of AI0 (the AI1’s is useless). As the same rule, if the AI2 is set as differential mode, then the AI2 and AI3 are combined to one channel and refer to the gain code and B/U of AI2 (the AI3’s is useless). The following examples show the scan sequence of differential mode.

Example 3

Suppose that the start scan input channel is AI2 and the stop scan input channel is AI8. If AI2 is differential mode (D), AI4 is D, AI6 is D and AI7 and AI8 are single-ended mode (S), then the scan sequence is AI2, AI4, AI6, AI7, AI8, AI2, AI4, AI6, AI7, AI8, AI2, AI4...

PCI-1712/1712L User’s Manual	– 86 –	Advantech Co., Ltd.
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Konica Minolta PCI-1712L user manual Appendix D

Contents

PCI-1712/1712L Users manual 1 MS/s, 12-bit, 16-ch High- Speed Multifunction CardVerifying your Installation Driver InstallationHardware Installation PCI-1712/1712L Quick StartDevice Installation March 2nd EditionPrinted in Taiwan Copyright3. Signal Connections Contents2. Installation 1. Introduction6. Calibration Appendix A. SpecificationAppendix B. Block Diagram Appendix C. Screw-terminal BoardDigital I/O registers - Write/Read BASE+28 Digital I/O configuration registers - Write/Read BASE+2AD/A Channel Data for Continuous Output Operation Mode Figures Figure 6-7 A/D Calibration Procedure Figure 6-5 A/D Calibration ProcedureFigure 6-6 A/D Calibration Procedure Figure 6-14 Adjusting registersTables Table D-22 Register for calibration command Table D-20 Register for digital I/O configurationTable D-21 Register for digital I/O configuration Table D-23 Calibration commandPage Chapter1 1.1 Features1. Introduction PCI-1712 1 MS/s High-Speed Multifunction CardChapter q Wiring board 1.2 Installation Guideq Wiring cable q PCI-1712/1712L DAS card q PCI-1712/1712L User’s ManualPCI-1712/1712L User’s Manual Figure 1-1 Installation Flow ChartChapter Wiring Boards 1.3 AccessoriesWiring Cable Chapter PCI-1712/1712L User’s Manual2.1 Unpacking 2. InstallationChapter2 2.2 Driver Installation Figure 2-1 The Setup Screen of Advantech Automation Software2.3 Hardware Installation Figure 2-2 Different options for Driver SetupStep 2 Remove the cover of your computer Figure 2-3 The device name listed on the Device Manager Figure 2-5 The I/O Device Installation dialog box 2.4 Device Setup & ConfigurationFigure 2-4 The Advantech Device Installation utility program Setting Up the DeviceConfiguring the Device Figure 2-7 The Device Setting dialog boxFigure 2-6 The “Devices Found” dialog box 0 to By inputting an external reference voltage xV, where 0=x=10you will get a output voltage range for unipolarTesting Analog Input Function 2.5 Device TestingFigure 2-9 Analog Input tab on the Device Test dialog box Testing Analog Output Function PCI-1712 only Figure 2-10 Analog Input tab on the Device Test dialog boxFigure 2-11 Analog Output tab on the Device Test dialog box Testing Digital Input FunctionTesting Digital Output Function Figure 2-12 Digital Input tab on the Device Test dialog boxFigure 2-13 Digital Output tab on the Device Test dialog box Testing Counter FunctionFigure 2-14 Digital output tab on the Device Test dialog box configure the Pulse Frequency by the scroll bar right below it3.1 Overview 3. Signal Connections3.2 I/O Connector Chapter3PCI-1712/1712L User’s Manual Figure 3-1 I/O connector pin assignments for the PCI-1712/1712LPins 20, 22~25, 54, 56~59 are not defined on PCI-1712L Direction Table 3-1 I/O Connector Signal Description PartSignal Name DescriptionReference Table 3-1 I/O Connector Signal Description PartSignal Name DirectionDirection Table 3-1 I/O Connector Signal Description PartSignal Name DescriptionSingle-ended Channel Connections 3.3 Analog Input ConnectionsFigure 3-2 Single-ended input channel connection Differential Channel Connectionssignal source Figure 3-3 Differential input channel connection - ground referenceFigure 3-4 Differential input channel connection - floating signal source3.4 Analog Output Connections Figure 3-5 Analog output connections3.5 Field Wiring Considerations 4.1 Programming Choices 4. Software OverviewChapter4 4.2 DLL Driver Programming Roadmap q Visual C++ q Visual Basic q Delphi q C++ Builderq Digital Input/Output Function Group q Counter Function Group q Temperature Measurement Function Group q Alarm Function Groupq Analog Iutput Function Group q Analog Output Function Group q Port Function Group q Communication Function GroupChapter PCI-1712/1712L User’s ManualChapter5 5.1 Analog Input Features5. Principles of Operation Table 5-1 Gains and Analog Input Rangeq Single Value Acquisition Mode Figure 5-1 Post-Trigger Acquisition Mode Figure 5-2 Delay-Trigger Acquisition ModeFigure 5-3 About-Trigger Acquisition Mode Figure 5-4 Pre-Trigger Acquisition Mode w Internal A/D sample clock with 16-bit CounterFigure 5-5 PCI-1712/1712L Sample Clock Source w Software trigger w External digital TTL trigger, andVoltage Ranges Table 5-2 Analog Input Data FormatTable 5-3 The corresponding Full Scale values for various Input q Analog Threshold Trigger5.2 Analog Output Features channel Chapter Table 5-5 The corresponding Full Scale values for various Output 5.3 Digital I/O FeaturesTable 5-4 Analog Output Data Format Analog Output Data Format5.4 Counter/Timer Features q Logic-low external gate input q Event counting Chapter Chapter Figure 5-6 Frequency measurement ChapterRead low byte Chapterdl= inportaddr21712+0x1c dh= inportaddr21712+0x1c8Chapter Figure 5-7 Pulse width measurement 65535-50000/1K = 15.535 secChapter CNT2’s gate input is lowChapter Show the duty ratio of positive6.1 VR Assignment 6. CalibrationChapter6 Figure 6-1 PCI-1712/1712L VR1 & TP56.2 A/D Calibration 6.3 D/A Calibration 6.4 Calibration Utility Figure 6-2 Selecting the device you want to calibrateA/D channel Auto-Calibration Figure 6-3 Warning message before start calibrationFigure 6-4 Auto A/D Calibration Dialog Box Step 5 The first A/D calibration procedure is enabled Fig Figure 6-5 A/D Calibration ProcedureFigure 6-6 A/D Calibration Procedure Step 6 The second A/D calibration procedure is enabled FigStep 7 The third A/D calibration procedure is enabled Fig Figure 6-7 A/D Calibration ProcedureFigure 6-8 A/D Calibration is finished Step 8 Auto-calibration is finished. See figStep 10 D/A channel 0 calibration is enabled Fig Figure 6-9 Range Selection in D/A CalibrationFigure 6-10 Calibrating D/A Channel Step 11 D/A channel 1 calibration is enabled Fig Figure 6-11 Calibrating D/A ChannelFigure 6-12 D/A Calibration is finished Step 12 Auto-calibration is finished FigFigure 6-13 Selecting Input Rage in Manual A/D Calibration panel A/D channel Manual-CalibrationFigure 6-14 Adjusting registers D/A channel Manual-Calibration Figure 6-15 & Figure 6-16 Selecting D/A Range andChoosing Output Voltage Figure 6-17 Adjusting registers Chapter PCI-1712/1712L User’s ManualPCI-1712 User’s Manual A. SpecificationAppendix A Digital Input /Output APPENDIX AAnalog Output PCI-1712 only PCI-1712/1712L User’s ManualCounter/Timer GeneralAPPENDIX A PCI-1712/1712L User’s ManualPCI BUS B. Block DiagramAppendix B A I T R G A O T R GAPPENDIX B PCI-1712/1712L User’s ManualC. 1 Introduction C. 2 FeaturesC. Screw-terminal Board AppendixCAPPENDIX C C.4 Pin AssignmentFigure C-2 CN2 pin assignments for the PCLD-8712 PCI-1712/1712L User’s ManualC.5 Single-ended Connections RDn RAn+RAn+1+RDn C.6 Differential Connectionsf3dB = 2π RAn+RAn+1 CDn D.1 Overview D. Register Structure and FormatAppendixD D.2 I/O Port Address MapPCI-1712/1712L User’s Manual Table D-1 PCI-1712/1712L register format PartAPPENDIX D APPENDIX D Table D-1 PCI-1712/1712L register format PartPCI-1712/1712L User’s Manual APPENDIX DTable D-1 PCI-1712/1712L register format Part Table D-2 Register for channel number and A/D data D.3 A/D Single Value Acquisition - Write BASE+0D.4 Channel and A/D data - Read BASE + D.5 A/D Channel Range Setting - Write BASE+2 Table D-3 Register for A/D channel range settingTable D-5 Register for multiplexer control D.6 MUX Control - Write BASE+4Table D-4 Gain Codes for the PCI-1712/1712L STR3 ~ STR0APPENDIX D Table D-6 Register for A/D control/status D.7 A/D Control/Status RegisterWrite/Read BASE+6 Analog input acquisition mode registerTable D-7 Analog Input Acquisition Mode This bit is used to select the A/D sample clock sourceClear interrupt D.8 Clear interrupt and FIFO - Write BASE+8Table D-8 Register for clear interrupt and FIFO D. 9 Interrupt and FIFO status - Read BASE+8 Table D-9 Register for interrupt and FIFO statusD.10 D/A control/status register - Write/Read BASE+A Table D-10 Register for D/A controlD/A channel 1 unipolar or bipolar output Table D-11 Analog output operation modeDA1U/B DACLKD.11 D/A Channel 0/1 Data - Write BASE+C/E Table D-12 Register for D/A channel 0/1 dataD.12 82C54 Counter Chip 0 - Write/Read BASE+10 to Table D-13 Register for 82C54 counter chipD.13 82C54 counter chip 1 - Write/Read BASE+18 to 1E Table D-14 Register for 82C54 counter chipTable D-16 Table of Cn1 to Cn0 register D.14 Counter gate and clock control/status - Write/ Read BASE+20 toTable D-15 Register for counter gate and clock control/status Cn1 Cn0 = 1, 0, External clock is on connector CNTnCLK n = 0, 1Counter clock set register n = 0,1,2 Table D-17 Table of Gn1 to Gn0 registerCounter clock edge control register n = 0,1,2 Gn1 to Gn0 Counter gate source control register n = 0,1,2Counter gate polarity control register n = 0,1,2 Table D-19 Register for Digital I/O D.15 Digital I/O registers - Write/Read BASE+28Table D-18 Table for CLKSEL1 to CLKSEL0 register Table D-20 Register for digital I/O configuration D.16 Digital I/O configuration registers - Write/Read BASE+2AD.17 Calibration command registers - Write BASE+2C Table D-22 Register for calibration commandD7 to D0 Table D-23 Calibration commandCM3 to CM0 Calibration command Calibration dataTable D-24 Register for D/A channel data DA11 TO DA0 D/A data