Appendix D | Konica Minolta PCI-1712L specification

APPENDIX D

Table D-1: PCI-1712/1712L register format (Part 1)

Base

PCI-1712/1712L Register Format

Address

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

W

A/D single value acquisition

0

R

Channel and A/D data

AF

CH2

CH1

CH0

AD11

AD10

AD9

AD8

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

W

A/D channel range setting

2

S/D

B/U

G2

G1

G0

R

N/A

W

Multiplexer setting

4

STP3

STP2

STP1

STP0

STR3

STR2

STR1

STR0

R

N/A

A/D control register

W

AI_

DMA

AIO_

AD_

AD_

AD_

ADM2

ADM1

ADM0

TRGF

_TCF

CAL

TRE

TR

CLK

6

A/D status register

R

AI_

DMA

AD_

AD_

AD_

ADM2

ADM1

ADM0

TRGF

_TCF

TRE

TR

CLK

Clear interrupt and FIFO

W

CLR

CLR

Clear interrupt

_DAF

_ADF

8

Interrupt and FIFO status

R

D/A_

D/A_

D/A_

A/D_

A/D_

A/D_

INT_

F/F

F/H

F/E

F/F

F/H

F/E

F

D/A control register

W

AO_

DA_

DAM-

DAM-

DA1

DA1

DA1

DA_

DA0

DA0

TRGF

CLK

1

0

_U/B

_I/E

_5/10

U/B

_I/E

_5/10

A

D/A status register

R

AO_

DA_

DAM1

DAM0

DA1

DA1

DA1

DA_

DA0

DA0

TRGF

CLK

_U/B

_I/E

_5/10

U/B

_I/E

_5/10

W

D/A channel 0 data

C

DA11

DA10

DA9

DA8

DA7

DA6

DA5

DA4

DA3

DA2

DA1

DA0

N/A

R

D/A channel 1 data

W

DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0

E

N/A

R

PCI-1712/1712L User’s Manual	– 80 –	Advantech Co., Ltd.
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Konica Minolta PCI-1712L user manual Appendix D, Table D-1 PCI-1712/1712L register format Part

PCI-1712L, PCI-1712 specifications

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Contents

MS/s, 12-bit, 16-ch High- Speed Multifunction Card PCI-1712/1712L Quick Start Unpacking Device Installation Page Contents Calibration Appendix D. Register Structure and Format 100 Figures Auto A/D Calibration Dialog Box I/O Connector Signal Description Part Corresponding Full Scale values for various InputTable D-1PCI-1712/1712L register format Part Table D-2 Table D-3 102 100101 Page Features Introduction PCI-Bus Mastering Data Transfer Plug-and-Play FunctionOn-board Fifo Memory Automatic Channel/Gain/SD*/BU* Scanning Continuous Analog Output Installation GuideOn-board Programmable Multifunction Counter/Timer Installation Flow Chart Wiring Boards AccessoriesWiring Cable Chapter Installation Unpacking Driver Installation Setup Screen of Advantech Automation Software Hardware Installation Different options for Driver Setup Chapter Device name listed on the Device Manager Device Setup & Configuration Setting Up the Device Configuring the Device Devices Found dialog box For unipolar For bipolar Device Testing Testing Analog Input Function Testing Analog Output Function PCI-1712 only Testing Digital Input Function Testing Digital Output Function Testing Counter Function 14 Digital output tab on the Device Test dialog box Signal Connections I/O ConnectorOverview Pin Assignment I/O connector pin assignments for the PCI-1712/1712L Connector Signal Description I/O Connector Signal Description Part Signal Name Reference Direction Description Counter 0 Gate Input. This pin is for Differential Channel Connections Analog Input ConnectionsSingle-ended Channel Connections Chapter Differential input channel connection floating signal Source Analog Output Connections Analog output connections Field Wiring Considerations Software Overview Programming ChoicesDLL Driver Register-level Programming DLL Driver Programming Roadmap Programming Tools Troubleshooting DLL Driver Error Programming with DLL Driver Function Library Chapter Analog Input Features Principles of OperationAnalog Input Ranges and Gains Gains and Analog Input Range Analog Input Acquisition Modes Post-Trigger Acquisition Mode About-Trigger Acquisition Mode Pre-Trigger Acquisition Mode Sample Clock Sources PCI-1712/1712L Sample Clock Source Trigger Sources Analog Input Data Format Analog Input Data Format Analog Output Operation Modes Analog Output FeaturesAnalog Output Ranges Output Clock Sources Trigger Sources Analog Output Data Format Digital I/O FeaturesAnalog Output Data Format Counter/Timer Features Clock sources Gate Types and Sources Counter/timer operation modes Chapter Chapter Frequency measurement Chapter Chapter Pulse width measurement Internal, and gate use for pulse Show the duty ratio of positive Calibration VR Assignment A/D Calibration D/A Calibration Calibration Utility Selecting the device you want to calibrate Channel Auto-Calibration Auto A/D Calibration Dialog Box A/D Calibration Procedure A/D Calibration is finished Range Selection in D/A Calibration 11 Calibrating D/A Channel Channel Manual-Calibration 13 Selecting Input Rage in Manual A/D Calibration panel 14 Adjusting registers 15 & -16 Selecting D/A Range Choosing Output Voltage 17 Adjusting registers Chapter Specification Analog Input Analog Output PCI-1712 only Digital Input /Output Counter/Timer General Appendix a Block Diagram Block Diagram Appendix B Screw-terminal Board Board Layout Pin Assignment Figure C-2 CN2 pin assignments for the PCLD-8712 Single-ended Connections Differential Connections Register Structure and Format I/O Port Address Map Appendix D Table D-1 PCI-1712/1712L register format Part Base PCI-1712/1712L Register Format Address Channel data for continuous output operation mode 30 W A/D Single Value Acquisition Write BASE+0 Channel and A/D data Read Base +Data of A/D Conversion CH2 to CH0 Channel Number A/D Channel Range Setting Write BASE+2 Table D-3 Register for A/D channel range settingSingle-ended or Differential Bipolar or Unipolar MUX Control Write BASE+4 Table D-4 Gain Codes for the PCI-1712/1712LTable D-5 Register for multiplexer control Start Scan Channel Number Appendix D Table D-6 Register for A/D control/status Analog input acquisition mode registerA/D Control/Status Register Write/Read BASE+6 Sample clock source select register Trigger source control registerTrigger edge control register Analog I/O calibration bit Clear interrupt and Fifo Write BASE+8 Aitrgf Analog input trigger flagTable D-8 Register for clear interrupt and Fifo Clear A/D Fifo Interrupt and Fifo status Read BASE+8 Interrupt flagFifo empty flag Fifo half-full flag 10 D/A control/status register Write/Read BASE+A Table D-11 Analog output operation mode Channel 1 unipolar or bipolar outputClock source select register Aotrgf Analog output trigger flag Data 11 D/A Channel 0/1 Data Write BASE+C/ETable D-12 Register for D/A channel 0/1 data 12 82C54 Counter Chip 0 Write/Read BASE+10 to Table D-13 Register for 82C54 counter chip 13 82C54 counter chip 1 Write/Read BASE+18 to 1E Table D-14 Register for 82C54 counter chip Cn1 to Cn0 Counter clock source control register n = 0,1,2 Table D-16 Table of Cn1 to Cn0 register CPn Counter clock edge control register n = 0,1,2 CQn Counter clock set register n = 0,1,2Gn1 to Gn0 Counter gate source control register n = 0,1,2 Table D-17 Table of Gn1 to Gn0 register GRn Pulse width measurement reset register n = 0,1,2 GPn Counter gate polarity control register n = 0,1,2GQn Counter gate set register n = 0,1,2 GATEn Gate status n = 0,1,2 Digital I/O registers Write/Read BASE+28 GATESn Pulse width measurement status bit n = 0,1,2CLKSEL1 & 0 Counter internal clock select register DO15 to DO0 Digital output data register Digital I/O configuration registers Write/Read BASE+2A Calibration command registers Write BASE+2CDIOC1 to DIOC0 Digital I/O configuration register DI15 to DI0 Digital input data register D7 to D0 Calibration data CM3 to CM0 Calibration commandTable D-23 Calibration command Table D-24 Register for D/A channel data DA11 to DA0 D/A data