PCI-1712/1712L Users manual
1 MS/s, 12-bit, 16-ch High- Speed Multifunction Card
Verifying your Installation
Driver Installation
Hardware Installation
PCI-1712/1712L Quick Start
Device Installation
March
2nd Edition
Printed in Taiwan
Copyright
3. Signal Connections
Contents
2. Installation
1. Introduction
6. Calibration
Appendix A. Specification
Appendix B. Block Diagram
Appendix C. Screw-terminal Board
Digital I/O configuration registers - Write/Read BASE+2A
D/A Channel Data for Continuous Output Operation Mode
Digital I/O registers - Write/Read BASE+28
Figures
Figure 6-7 A/D Calibration Procedure
Figure 6-5 A/D Calibration Procedure
Figure 6-6 A/D Calibration Procedure
Figure 6-14 Adjusting registers
Tables
Table D-22 Register for calibration command
Table D-20 Register for digital I/O configuration
Table D-21 Register for digital I/O configuration
Table D-23 Calibration command
Page
Chapter1
1.1 Features
1. Introduction
PCI-1712 1 MS/s High-Speed Multifunction Card
Chapter
q Wiring board
1.2 Installation Guide
q Wiring cable
q PCI-1712/1712L DAS card q PCI-1712/1712L User’s Manual
Figure 1-1 Installation Flow Chart
Chapter
PCI-1712/1712L User’s Manual
1.3 Accessories
Wiring Cable
Wiring Boards
Chapter
PCI-1712/1712L User’s Manual
2. Installation
Chapter2
2.1 Unpacking
2.2 Driver Installation
Figure 2-1 The Setup Screen of Advantech Automation Software
2.3 Hardware Installation
Figure 2-2 Different options for Driver Setup
Step 2 Remove the cover of your computer
Figure 2-3 The device name listed on the Device Manager
Figure 2-5 The I/O Device Installation dialog box
2.4 Device Setup & Configuration
Figure 2-4 The Advantech Device Installation utility program
Setting Up the Device
Figure 2-7 The Device Setting dialog box
Figure 2-6 The “Devices Found” dialog box
Configuring the Device
0 to
By inputting an external reference voltage xV, where 0=x=10
you will get a output voltage range
for unipolar
2.5 Device Testing
Figure 2-9 Analog Input tab on the Device Test dialog box
Testing Analog Input Function
Testing Analog Output Function PCI-1712 only
Figure 2-10 Analog Input tab on the Device Test dialog box
Figure 2-11 Analog Output tab on the Device Test dialog box
Testing Digital Input Function
Testing Digital Output Function
Figure 2-12 Digital Input tab on the Device Test dialog box
Figure 2-13 Digital Output tab on the Device Test dialog box
Testing Counter Function
Figure 2-14 Digital output tab on the Device Test dialog box
configure the Pulse Frequency by the scroll bar right below it
3.1 Overview
3. Signal Connections
3.2 I/O Connector
Chapter3
Figure 3-1 I/O connector pin assignments for the PCI-1712/1712L
Pins 20, 22~25, 54, 56~59 are not defined on PCI-1712L
PCI-1712/1712L User’s Manual
Direction
Table 3-1 I/O Connector Signal Description Part
Signal Name
Description
Reference
Table 3-1 I/O Connector Signal Description Part
Signal Name
Direction
Direction
Table 3-1 I/O Connector Signal Description Part
Signal Name
Description
Single-ended Channel Connections
3.3 Analog Input Connections
Figure 3-2 Single-ended input channel connection
Differential Channel Connections
signal source
Figure 3-3 Differential input channel connection - ground reference
Figure 3-4 Differential input channel connection - floating signal
source
3.4 Analog Output Connections
Figure 3-5 Analog output connections
3.5 Field Wiring Considerations
4. Software Overview
Chapter4
4.1 Programming Choices
4.2 DLL Driver Programming Roadmap
q Visual C++ q Visual Basic q Delphi q C++ Builder
q Digital Input/Output Function Group q Counter Function Group
q Temperature Measurement Function Group q Alarm Function Group
q Analog Iutput Function Group q Analog Output Function Group
q Port Function Group q Communication Function Group
Chapter
PCI-1712/1712L User’s Manual
Chapter5
5.1 Analog Input Features
5. Principles of Operation
Table 5-1 Gains and Analog Input Range
q Single Value Acquisition Mode
Figure 5-1 Post-Trigger Acquisition Mode
Figure 5-2 Delay-Trigger Acquisition Mode
Figure 5-3 About-Trigger Acquisition Mode
Figure 5-4 Pre-Trigger Acquisition Mode
w Internal A/D sample clock with 16-bit Counter
Figure 5-5 PCI-1712/1712L Sample Clock Source
w Software trigger w External digital TTL trigger, and
Voltage Ranges
Table 5-2 Analog Input Data Format
Table 5-3 The corresponding Full Scale values for various Input
q Analog Threshold Trigger
5.2 Analog Output Features
channel
Chapter
Table 5-5 The corresponding Full Scale values for various Output
5.3 Digital I/O Features
Table 5-4 Analog Output Data Format
Analog Output Data Format
5.4 Counter/Timer Features
q Logic-low external gate input
q Event counting
Chapter
Chapter
Figure 5-6 Frequency measurement
Chapter
Read low byte
Chapter
dl= inportaddr21712+0x1c
dh= inportaddr21712+0x1c8
Chapter
Figure 5-7 Pulse width measurement
65535-50000/1K = 15.535 sec
Chapter
CNT2’s gate input is low
Chapter
Show the duty ratio of positive
6.1 VR Assignment
6. Calibration
Chapter6
Figure 6-1 PCI-1712/1712L VR1 & TP5
6.2 A/D Calibration
6.3 D/A Calibration
6.4 Calibration Utility
Figure 6-2 Selecting the device you want to calibrate
Figure 6-3 Warning message before start calibration
Figure 6-4 Auto A/D Calibration Dialog Box
A/D channel Auto-Calibration
Step 5 The first A/D calibration procedure is enabled Fig
Figure 6-5 A/D Calibration Procedure
Figure 6-6 A/D Calibration Procedure
Step 6 The second A/D calibration procedure is enabled Fig
Step 7 The third A/D calibration procedure is enabled Fig
Figure 6-7 A/D Calibration Procedure
Figure 6-8 A/D Calibration is finished
Step 8 Auto-calibration is finished. See fig
Figure 6-9 Range Selection in D/A Calibration
Figure 6-10 Calibrating D/A Channel
Step 10 D/A channel 0 calibration is enabled Fig
Step 11 D/A channel 1 calibration is enabled Fig
Figure 6-11 Calibrating D/A Channel
Figure 6-12 D/A Calibration is finished
Step 12 Auto-calibration is finished Fig
Figure 6-13 Selecting Input Rage in Manual A/D Calibration panel
A/D channel Manual-Calibration
Figure 6-14 Adjusting registers
Figure 6-15 & Figure 6-16 Selecting D/A Range and
Choosing Output Voltage
D/A channel Manual-Calibration
Figure 6-17 Adjusting registers
Chapter
PCI-1712/1712L User’s Manual
A. Specification
Appendix A
PCI-1712 User’s Manual
Digital Input /Output
APPENDIX A
Analog Output PCI-1712 only
PCI-1712/1712L User’s Manual
Counter/Timer
General
APPENDIX A
PCI-1712/1712L User’s Manual
PCI BUS
B. Block Diagram
Appendix B
A I T R G A O T R G
APPENDIX B
PCI-1712/1712L User’s Manual
C. 1 Introduction
C. 2 Features
C. Screw-terminal Board
AppendixC
APPENDIX C
C.4 Pin Assignment
Figure C-2 CN2 pin assignments for the PCLD-8712
PCI-1712/1712L User’s Manual
C.5 Single-ended Connections
C.6 Differential Connections
f3dB = 2π RAn+RAn+1 CDn
RDn RAn+RAn+1+RDn
D.1 Overview
D. Register Structure and Format
AppendixD
D.2 I/O Port Address Map
Table D-1 PCI-1712/1712L register format Part
APPENDIX D
PCI-1712/1712L User’s Manual
APPENDIX D
Table D-1 PCI-1712/1712L register format Part
APPENDIX D
Table D-1 PCI-1712/1712L register format Part
PCI-1712/1712L User’s Manual
D.3 A/D Single Value Acquisition - Write BASE+0
D.4 Channel and A/D data - Read BASE +
Table D-2 Register for channel number and A/D data
D.5 A/D Channel Range Setting - Write BASE+2
Table D-3 Register for A/D channel range setting
Table D-5 Register for multiplexer control
D.6 MUX Control - Write BASE+4
Table D-4 Gain Codes for the PCI-1712/1712L
STR3 ~ STR0
APPENDIX D
Table D-6 Register for A/D control/status
D.7 A/D Control/Status Register
Write/Read BASE+6
Analog input acquisition mode register
Table D-7 Analog Input Acquisition Mode
This bit is used to select the A/D sample clock source
D.8 Clear interrupt and FIFO - Write BASE+8
Table D-8 Register for clear interrupt and FIFO
Clear interrupt
D. 9 Interrupt and FIFO status - Read BASE+8
Table D-9 Register for interrupt and FIFO status
D.10 D/A control/status register - Write/Read BASE+A
Table D-10 Register for D/A control
D/A channel 1 unipolar or bipolar output
Table D-11 Analog output operation mode
DA1U/B
DACLK
D.11 D/A Channel 0/1 Data - Write BASE+C/E
Table D-12 Register for D/A channel 0/1 data
D.12 82C54 Counter Chip 0 - Write/Read BASE+10 to
Table D-13 Register for 82C54 counter chip
D.13 82C54 counter chip 1 - Write/Read BASE+18 to 1E
Table D-14 Register for 82C54 counter chip
Table D-16 Table of Cn1 to Cn0 register
D.14 Counter gate and clock control/status - Write/ Read BASE+20 to
Table D-15 Register for counter gate and clock control/status
Cn1 Cn0 = 1, 0, External clock is on connector CNTnCLK n = 0, 1
Counter clock set register n = 0,1,2
Table D-17 Table of Gn1 to Gn0 register
Counter clock edge control register n = 0,1,2
Gn1 to Gn0 Counter gate source control register n = 0,1,2
Counter gate polarity control register n = 0,1,2
D.15 Digital I/O registers - Write/Read BASE+28
Table D-18 Table for CLKSEL1 to CLKSEL0 register
Table D-19 Register for Digital I/O
Table D-20 Register for digital I/O configuration
D.16 Digital I/O configuration registers - Write/Read BASE+2A
D.17 Calibration command registers - Write BASE+2C
Table D-22 Register for calibration command
D7 to D0
Table D-23 Calibration command
CM3 to CM0 Calibration command
Calibration data
Table D-24 Register for D/A channel data
DA11 TO DA0 D/A data
