Omega Vehicle Security 1400 Theory of Operation, Register Access, Register Chart Mask Registers

Registers, Data Formats, & Queries						Appendix C
		Register Chart
	Status and Event Reporting
	Registers			Command Type
	Register	Access	Read	Write	Clear
	CSR	Read/Clear	U2	N/A	U2
	Calibration Status
	ESC	Read/Clear	E?	N/A	E?
	Error Source
	ESR	Read/Clear	U0	N/A	U0
	Event Status
	STB	Read	U1	N/A	N/A
	Status Byte		(SPOLL)
		Register Chart
	Mask Registers			Command Type
	Register	Access	Read	Write	Clear
	ESE	Read/Write/	N?	Nmmm	N0
	Event Status	Clear		(See
	Enable			Note)
	SRE	Read/Write/	M?	Mmmm	M0
	Service Request	Clear		(See
	Enable			Note)
	Note: The mmm defines the contents of the register to be written.

Theory of Operation

The following figure shows the general operation and relationship between the status reporting and mask registers. Each register is part of a hierarchy of registers where operations on higher registers will affect the contents of lower registers in the chain. This hierarchical approach provides the ability to have varying levels of status reporting. The lowest levels give general status information while the higher levels give more details of the particular events in question.

At the lowest level in this chain is the Status Byte Register. This register may be accessed real-time by the controller via a SPOLL (IEEE-488 only) command. This allows quick response of certain critical operational status conditions contained in the Status Byte Register (STB). However, since this register is the lowest register in the chain, every other status register in the system, either directly or indirectly, has access to the STB register via the Event Status Register Bit (ESB) in the STB register. This gives these other status registers the ability (although not detailed) to quickly report their status to the controller.

The Event Status Enable (ESE) Register may be used to define which bits in the Event Status Register will be mapped into the Event Status Register Bit (ESB) in the STB. The bits in the ESE represent an exact image of the bits in the ESR. When a condition is set in the ESR its image bit is checked in the ESE. If enabled the ESB bit in the STB is set.

The Service Request Enable (SRE) register may be used to define those conditions in the STB which will generate a Service Request (SRQ). The bits in the SRE represent an exact image of the bits in the STB accept for Service Request Bit. When a condition is set in the STB its image bit is checked in the SRE. If enabled, ChartScan will generate a Service Request (SRQ).

In the same fashion that the setting of events (or conditions) affects the lower levels of registers in the chain, the clearing of events (or conditions) in the higher level registers, will cause the clearing conditions in the lower level registers.

The following sections describe in detail the contents and operation of these registers. More information on these registers can also be found in the Command Reference section under the M,N,U and E? commands relating to these registers.

C-12 ChartScan User’s Manual