![](/images/new-backgrounds/1204826/20482629x1.webp)
Unbuffered DIMM
datasheet
Rev. 1.0
DDR3L SDRAM
11.3 AC and DC Logic Input Levels for Differential Signals
11.3.1 Differential Signals Definition
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| tDVAC | ||||||||||||||||||||||||||||
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| VIH.DIFF.AC.MIN |
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| VIH.DIFF.MIN | ||||||||||||||||||||||||||||||||||||||||||||
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| 0.0 |
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(i.e. |
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| half cycle | |||||||||||||||||||||||||||||||||||
Voltage |
| VIL.DIFF.MAX |
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Input |
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Differential |
| VIL.DIFF.AC.MAX |
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| tDVAC | ||||||||||||
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| time | |||
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Figure 3. Definition of differential ac-swing and "time above ac level" tDVAC
11.3.2 Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS)
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Symbol | Parameter | 1.35V | 1.5V | unit | NOTE | ||
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| min | max | min | max |
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VIHdiff | differential input high | +0.18 | NOTE 3 | +0.20 | NOTE 3 | V | 1 |
VILdiff | differential input low | NOTE 3 | NOTE 3 | V | 1 | ||
VIHdiff(AC) | differential input high ac | 2 x (VIH(AC) - VREF) | NOTE 3 | 2 x (VIH(AC) - VREF) | NOTE 3 | V | 2 |
VILdiff(AC) | differential input low ac | NOTE 3 | 2 x (VIL(AC) - VREF) | NOTE 3 | 2 x (VIL(AC) - VREF) | V | 2 |
NOTE :
1.Used to define a differential signal
2.for CK - CK use VIH/VIL(AC) of ADD/CMD and VREFCA; for DQS - DQS use VIH/VIL(AC) of DQs and VREFDQ; if a reduced
3.These values are not defined, however they
nals as well as the limitations for overshoot and undershoot. Refer to "overshoot and Undersheet Specification"
- 15 -