Samsung M391B5773DH0, M391B5273DH0 specifications Input/Output Capacitance, Czq

Unbuffered DIMM

datasheet

Rev. 1.0

DDR3L SDRAM

15. Input/Output Capacitance

[ Table 16 ] Input/Output Capacitance

	Parameter	Symbol	DDR3-800		DDR3-1066		DDR3-1333		DDR3-1600		Units	NOTE
			Min	Max	Min	Max	Min	Max	Min	Max
				1.35V
Input/output capacitance		CIO	1.5	2.5	1.5	2.5	1.5	2.3	1.2	2.3	pF	1,2,3
(DQ, DM, DQS, DQS, TDQS, TDQS)
Input capacitance		CCK	0.8	1.6	0.8	1.6	TBD	TBD	TBD	TBD	pF	2,3
(CK and CK)
Input capacitance delta		CDCK	0	0.15	0	0.15	TBD	TBD	TBD	TBD	pF	2,3,4
(CK and CK)
Input capacitance		CI	0.75	1.3	0.75	1.3	0.75	1.3	0.75	1.3	pF	2,3,6
(All other input-only pins)
Input/Output capacitance delta		CDDQS	0	0.2	0	0.2	TBD	TBD	TBD	TBD	pF	2,3,5
(DQS and DQS)
Input capacitance delta		CDI_CTRL	-0.5	0.3	-0.5	0.3	TBD	TBD	TBD	TBD	pF	2,3,7,8
(All control input-only pins)
Input capacitance delta		CDI_ADD_CMD	-0.5	0.5	-0.5	0.5	TBD	TBD	TBD	TBD	pF	2,3,9,10
(all ADD and CMD input-only pins)
Input/output capacitance delta		CDIO	-0.5	0.3	-0.5	0.3	TBD	TBD	TBD	TBD	pF	2,3,11
(DQ, DM, DQS, DQS, TDQS, TDQS)
Input/output capacitance of ZQ pin		CZQ	-	3	-	3	TBD	TBD	TBD	TBD	pF	2, 3, 12
				1.5V
Input/output capacitance		CIO	1.5	3.0	1.5	2.7	1.5	2.5	1.4	2.3	pF	1,2,3
(DQ, DM, DQS, DQS, TDQS, TDQS)
Input capacitance		CCK	0.8	1.6	0.8	1.6	0.8	1.4	0.8	1.4	pF	2,3
(CK and CK)
Input capacitance delta		CDCK	0	0.15	0	0.15	0	0.15	0	0.15	pF	2,3,4
(CK and CK)
Input capacitance		CI	0.75	1.5	0.75	1.5	0.75	1.3	0.75	1.3	pF	2,3,6
(All other input-only pins)
Input capacitance delta		CDDQS	0	0.2	0	0.2	0	0.15	0	0.15	pF	2,3,5
(DQS and DQS)
Input capacitance delta		CDI_CTRL	-0.5	0.3	-0.5	0.3	-0.4	0.2	-0.4	0.2	pF	2,3,7,8
(All control input-only pins)
Input capacitance delta		CDI_ADD_CMD	-0.5	0.5	-0.5	0.5	-0.4	0.4	-0.4	0.4	pF	2,3,9,10
(all ADD and CMD input-only pins)
Input/output capacitance delta		CDIO	-0.5	0.3	-0.5	0.3	-0.5	0.3	-0.5	0.3	pF	2,3,11
(DQ, DM, DQS, DQS, TDQS, TDQS)
Input/output capacitance of ZQ pin		CZQ	-	3	-	3	-	3	-	3	pF	2, 3, 12

NOTE : This parameter is Component Input/Output Capacitance so that is different from Module level Capacitance.

1.Although the DM, TDQS and TDQS pins have different functions, the loading matches DQ and DQS

2.This parameter is not subject to production test. It is verified by design and characterization.

The capacitance is measured according to JEP147("PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER( VNA)") with VDD, VDDQ, VSS, VSSQ applied and all other pins floating (except the pin under test, CKE, RESET and ODT as necessary). VDD=VDDQ=1.5V, VBIAS=VDD/2 and on-die termination off.

3.This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here

4.Absolute value of CCK-CCK

5.Absolute value of CIO(DQS)-CIO(DQS)

6.CI applies to ODT, CS, CKE, A0-A15, BA0-BA2, RAS, CAS, WE.

7.CDI_CTRL applies to ODT, CS and CKE

8.CDI_CTRL=CI(CTRL)-0.5*(CI(CLK)+CI(CLK))

9.CDI_ADD_CMD applies to A0-A15, BA0-BA2, RAS, CAS and WE

10.CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK))

11.CDIO=CIO(DQ,DM) - 0.5*(CIO(DQS)+CIO(DQS))

12.Maximum external load capacitance on ZQ pin: 5pF

- 25 -