![](/images/new-backgrounds/1204826/20482643x1.webp)
Unbuffered DIMM
datasheet
Rev. 1.0
DDR3L SDRAM
13. IDD specification definition
Symbol |
|
| Description | ||||||||||||||||||||
| Operating One Bank | ||||||||||||||||||||||
IDD0 | CKE: High; External clock: On; tCK, nRC, nRAS, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0; | CS | : High between ACT and PRE; | ||||||||||||||||||||
Command, Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0; Bank Activity: Cycling with one bank active at a time: | |||||||||||||||||||||||
| 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pat- | ||||||||||||||||||||||
| tern | ||||||||||||||||||||||
| Operating One Bank | ||||||||||||||||||||||
IDD1 | CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0; | CS | : High between ACT, RD | ||||||||||||||||||||
and PRE; Command, Address, Bank Address Inputs, Data IO: partially toggling ; DM:stable at 0; Bank Activity: Cycling with one bank active at a time: | |||||||||||||||||||||||
| 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pat- | ||||||||||||||||||||||
| tern | ||||||||||||||||||||||
|
| ||||||||||||||||||||||
| Precharge Standby Current | ||||||||||||||||||||||
IDD2N | CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0; | CS | : stable at 1; Command, Address, Bank | ||||||||||||||||||||
Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode | |||||||||||||||||||||||
| |||||||||||||||||||||||
| Registers2); ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern | ||||||||||||||||||||||
| Precharge | ||||||||||||||||||||||
IDD2P0 | CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0; | CS | : stable at 1; Command, Address, Bank | ||||||||||||||||||||
Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2); | |||||||||||||||||||||||
| |||||||||||||||||||||||
| ODT Signal: stable at 0; Precharge Power Down Mode: Slow Exit3) | ||||||||||||||||||||||
| Precharge | ||||||||||||||||||||||
IDD2P1 | CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0; | CS | : stable at 1; Command, Address, Bank | ||||||||||||||||||||
Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2); | |||||||||||||||||||||||
| |||||||||||||||||||||||
| ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exit3) | ||||||||||||||||||||||
| Precharge Quiet Standby Current | ||||||||||||||||||||||
IDD2Q | CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0; | CS | : stable at 1; Command, Address, Bank | ||||||||||||||||||||
Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2); | |||||||||||||||||||||||
| |||||||||||||||||||||||
| ODT Signal: stable at 0 | ||||||||||||||||||||||
|
| ||||||||||||||||||||||
| Active Standby Current | ||||||||||||||||||||||
IDD3N | CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0; | CS | : stable at 1; Command, Address, Bank | ||||||||||||||||||||
Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode | |||||||||||||||||||||||
| |||||||||||||||||||||||
| Registers2); ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern | ||||||||||||||||||||||
| Active | ||||||||||||||||||||||
IDD3P | CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0; | CS | : stable at 1; Command, Address, Bank | ||||||||||||||||||||
Address Inputs: stable at 0; Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers2); ODT | |||||||||||||||||||||||
| |||||||||||||||||||||||
| Signal: stable at 0 | ||||||||||||||||||||||
|
| ||||||||||||||||||||||
| Operating Burst Read Current | ||||||||||||||||||||||
IDD4R | CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0; | CS | : High between RD; Command, Address, | ||||||||||||||||||||
Bank Address Inputs: partially toggling ; Data IO: seamless read data burst with different data between one burst and the next one ; DM:stable at 0; Bank | |||||||||||||||||||||||
| Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable | ||||||||||||||||||||||
| at 0; Pattern Details: Refer to Component Datasheet for detail pattern | ||||||||||||||||||||||
| Operating Burst Write Current | ||||||||||||||||||||||
IDD4W | CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0; | CS | : High between WR; Command, Address, | ||||||||||||||||||||
Bank Address Inputs: partially toggling ; Data IO: seamless write data burst with different data between one burst and the next one ; DM: stable at 0; Bank | |||||||||||||||||||||||
| Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable | ||||||||||||||||||||||
| at HIGH; Pattern Details: Refer to Component Datasheet for detail pattern | ||||||||||||||||||||||
| Burst Refresh Current | ||||||||||||||||||||||
IDD5B | CKE: High; External clock: On; tCK, CL, nRFC: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0; | CS | : High between REF; Command, | ||||||||||||||||||||
Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING;DM:stable at 0; Bank Activity: REF command every nRFC ; Output Buffer and | |||||||||||||||||||||||
| |||||||||||||||||||||||
| RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern | ||||||||||||||||||||||
| Self Refresh Current: Normal Temperature Range | ||||||||||||||||||||||
IDD6 | TCASE: 0 - 85°C; Auto | CK: |
|
| |||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| ||
LOW; CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0; | |||||||||||||||||||||||
| |||||||||||||||||||||||
| Bank Activity: | ||||||||||||||||||||||
|
| ||||||||||||||||||||||
IDD6ET | TCASE: 0 - 95°C; Auto | CK: |
| ||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| ||
LOW; CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0; | |||||||||||||||||||||||
| |||||||||||||||||||||||
| Bank Activity: Extended Temperature | ||||||||||||||||||||||
| Operating Bank Interleave Read Current | ||||||||||||||||||||||
| CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: | CS | : High | ||||||||||||||||||||
IDD7 | between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling ; Data IO: read data bursts with different data between one burst and | ||||||||||||||||||||||
| the next one ; DM:stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing ; Output Buffer and RTT: | ||||||||||||||||||||||
| Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern | ||||||||||||||||||||||
| RESET Low Current | ||||||||||||||||||||||
IDD8 | RESET : Low; External clock : off; CK and | CK | : LOW; CKE : FLOATING ; | CS, | Command, Address, Bank Address, Data IO : FLOATING ; ODT Signal : | ||||||||||||||||||
| FLOATING |
- 22 -