Samsung M391B5273DH0, M391B5773DH0 specifications Single-ended Output Slew Rate, SRQse

Unbuffered DIMM

datasheet

Rev. 1.0

DDR3L SDRAM

12.3 Single-ended Output Slew Rate

With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for single ended signals as shown in below.

[ Table 12 ] Single ended Output slew rate definition

Description	Measured		Defined by
	From	To
Single ended output slew rate for rising edge	VOL(AC)	VOH(AC)	VOH(AC)-VOL(AC)
			Delta TRse
Single ended output slew rate for falling edge	VOH(AC)	VOL(AC)	VOH(AC)-VOL(AC)
			Delta TFse

NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.

[ Table 13 ] Single ended output slew rate

Parameter	Symbol	Operation	DDR3-800		DDR3-1066		DDR3-1333		DDR3-1600		Units
		Voltage	Min	Max	Min	Max	Min	Max	Min	Max
Single ended output slew rate	SRQse	1.35V	1.75	51)	1.75	51)	1.75	51)	1.75	51)	V/ns
		1.5V	2.5	5	2.5	5	2.5	5	2.5	5	V/ns

Description : SR : Slew Rate

Q : Query Output (like in DQ, which stands for Data-in, Query-Output)

se : Single-ended Signals For Ron = RZQ/7 setting

NOTE : 1) In two cased, a maximum slew rate of 6V/ns applies for a single DQ signal within a byte lane.

-Case_1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low of low to high) while all remaining DQ signals in the same byte lane are static (i.e they stay at either high or low).

-Case_2 is defined for a single DQ signals in the same byte lane are switching into the opposite direction (i.e. from low to high or high to low respectively). For the remaining DQ signal switching into the opposite direction, the regular maximum limit of 5 V/ns applies.

VOHdiff(AC)

VTT

VOLdiff(AC)

delta TFdiff delta TRdiff

Figure 7. Single-ended output slew rate definition

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