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Samsung M391B5773DH0 specifications 18.2 256Mbx8 based 512Mx72 Module 2 Ranks M391B5273DH0

Models: M391B5773DH0 M391B5273DH0

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Unbuffered DIMM

datasheet

Rev. 1.0

DDR3L SDRAM

18.2 256Mbx8 based 512Mx72 Module (2 Ranks) - M391B5273DH0

9.50

Units : Millimeters

	133.35 ± 0.15
		± 0.1
	128.95	(4X)3.00
		(4X)3.00
	SPD	17.30	± 0.15
		17.30	30.00
(2)		2.30
2.50		2.30
2.50
54.675
A	B		Max 4.0
47.00		71.00	Max 4.0
47.00		71.00

1.270 ± 0.10

5.00

3.80

1.50±0.10

2.50

Detail A

2.50 ± 0.20

0.80 ± 0.05		2x 2.10 ± 0.15

0.2 ± 0.15

1.00

Detail B

The used device is 256M x8 DDR3L SDRAM, FBGA. DDR3 SDRAM Part NO : K4B2G0846D-HY∗∗

*NOTE : Tolerances on all dimensions ±0.15 unless otherwise specified.

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Samsung M391B5773DH0 specifications 18.2 256Mbx8 based 512Mx72 Module 2 Ranks M391B5273DH0

Contents

Datasheet Rev History Draft DateTable Of Contents Key Features Address ConfigurationDDR3L Unbuffered Dimm Ordering Information Speed DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 UnitX72 Dimm Pin Configurations Front side/Back side Pin Front BackPin Description SPD and Thermal Sensor for ECC UDIMMsPin Name Description Symbol Type Function Input/Output Functional DescriptionAddress Mirroring Feature Dram Pin Wiring MirroringConnector Pin Dram Pin Rank Function Block Diagram SCL SDA Event SA0 SA1 SA2D14 Dram Component Operating Temperature Range Absolute Maximum RatingsAC & DC Operating Conditions Absolute Maximum DC Ratings11.1 AC & DC Logic Input Levels for Single-ended Signals AC & DC Input Measurement LevelsVIH.DQDC90 Vref Tolerances Illustration of Vrefdc tolerance and Vref ac-noise limitsAC and DC Logic Input Levels for Differential Signals Differential Signals Definition35V TBD Single-ended Requirements for Differential Signals TimeDifferential Input Cross Point Voltage CK, DQS VselSlew Rate Definition for Single Ended Input Signals Slew rate definition for Differential Input SignalsAC & DC Output Measurement Levels Single Ended AC and DC Output LevelsSingle-ended Output Slew Rate SRQseDifferential Output Slew Rate Differential output slew rate definitionIDD specification definition Symbol DescriptionDatasheet DDR3-1066 DDR3-1333 DDR3-1600 Symbol 11-11-11 Unit IDD Spec TableM391B5773DH0 2GB256Mx72 Module M391B5273DH0 4GB512Mx72 ModuleInput/Output Capacitance CZQElectrical Characteristics and AC timing Refresh Parameters by Device DensityDDR3-1066 Speed Bins Speed Bin Table Notes DDR3-1600 Speed Bins CL-nRCD-nRPDatasheet Timing Parameters by Speed Grade Timing Parameters by Speed BinMIN MAX Reset Timing Jitter Notes Timing Parameter Notes ZQCorrection TSens x Tdriftrate + VSens x VdriftratePhysical Dimensions 18.1 256Mbx8 based 256Mx72 Module 1 Rank M391B5773DH018.2 256Mbx8 based 512Mx72 Module 2 Ranks M391B5273DH0