SMSC COM20020 FIGURE 13 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; WRITE CYCLE

52
A0-A2
VALID DATA
VALID
D0-D7
t1
t3
t5
t6
t7
Parameter
Address Setup to nWR Active
nCS Setup to WR Active
Cycle Time (nWR Low to Next Time Low)**
Valid Data Setup to nWR High
Data Hold from nWR High
min
15
5
10
max
4T*
30**
units
nS
nS
nS
nS
nS
nCS
t6
t1
t7
t3
t5
T is the Arbitration Clock Period.
T is identical to XTAL1 if SLOW ARB = 0,
*
T is twice XTAL1 period if SLOW ARB = 1
t4
t4 nCS Hold from nWR Inactive 0nS
t2
t2 Address Hold from nWR Inactive 10 nS
The Microcontroller typically accesses the COM20020 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20020 cycles.
Note 2
t5**
Note 1:
Note 2: Any cycle occurring after a write to the Address Pointer Low Register
requires a minimum of 4T from the trailing edge of nWR to the leading edge
of the next nWR.
nWR
**nCS may become active after control becomes active, but the data setup time will now
be 30 nS measured from the later of nCS falling or Valid Data available.
FIGURE 13 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; WRITE CYCLE