![](/images/new-backgrounds/1306248/306248109x1.webp)
nTXEN
t1
nPULSE1
nPULSE2 (Internal Clk)
RXIN
t9
t4
t10
t3
t2
t8
LAST BIT
(400 nS BIT TIME)
t5
t6
t7
t11
| Parameter | min | typ | max | units |
|
|
|
|
|
|
t1 | nPULSE2 High to nTXEN Low | 0 |
| 50 | nS |
t2 | nPULSE1 Pulse Width |
| 200* |
| nS |
t3 | nPULSE1 Period | 400* |
| nS | |
t4 | nPULSE2 Low to nPULSE1 Low | 100* | 25 | nS | |
t5 | nPULSE2 High Time |
|
| nS | |
t6 | nPULSE2 Low Time |
| 100* |
| nS |
t7 | nPULSE2 Period |
| 200* | 50 | nS |
t8 | nPULSE2 High to nTXEN High | 0 |
| nS | |
t9 | (First rising edge on nPULSE2 after Last Bit Time) | 650 |
| 750 | nS |
nTXEN Low to first nPULSE1 Low** |
| ||||
t10 | RXIN Pulse Width | 10 | 200* |
| nS |
t11 | RXIN Period |
| 400* |
| nS |
*t5,t6 = 2 x (crystal period) for clock frequencies other than 20 MHz.
*t2,t7,t10 = 4 x (crystal period) for clock frequencies other than 20 MHz.
*t3,t11 = 8 x (crystal period) for clock frequencies other than 20 MHz.
This period applies to data of two consecutive one's.
** t9: For clock frequencies other than 20 MHz, t9 = 14 x (clock period) + 50 nsec.
FIGURE 15 - BACKPLANE MODE TRANSMIT OR RECEIVE TIMING (These signals are to and from the differential driver or the cable)
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