A0/nMUX

 

A1

 

A2/BALE

ADDRESS

 

 

DECODING

 

CIRCUITRY

AD0-AD2,

D3-D7

2K x 8

RAM

ADDITIONAL

REGISTERS

nINTR

STATUS/

 

 

 

COMMAND

 

 

nPULSE1

 

REGISTER

MICRO-

TX/RX

nPULSE2

 

 

SEQUENCER

nTXEN

 

 

LOGIC

 

 

AND

 

 

 

RXIN

 

 

WORKING

 

 

 

 

 

nRESET IN

RESET

REGISTERS

 

 

LOGIC

 

 

 

 

 

 

 

 

 

 

OSCILLATOR

XTAL1

 

 

 

XTAL2

 

 

 

 

nRD/nDS

 

 

 

 

nWR/DIR

BUS

 

 

 

 

 

 

 

nCS

ARBITRATION

 

 

 

 

CIRCUITRY RECONFIGURATION

NODE ID

 

 

 

TIMER

LOGIC

 

FIGURE 6 - INTERNAL BLOCK DIAGRAM

18

Page 18
Image 18
SMSC COM20020 manual Internal Block Diagram