18
MICRO-
SEQUENCER
AND
WORKING
REGISTERS
STATUS/
COMMAND
REGISTER
RESET
LOGIC
RECONFIGURATION
TIMER NODE ID
LOGIC
OSCILLATOR
TX/RX
LOGIC
ADDITIONAL
REGISTERS
ADDRESS
DECODING
CIRCUITRY 2K x 8
AD0-AD2,
BUS
ARBITRATION
CIRCUITRY
nPULSE1
nPULSE2
nTXEN
XTAL1
XTAL2
nINTR
nRESET IN
RAM
A0/nMUX
A1
A2/BALE
nRD/nDS
nWR/DIR
nCS
D3-D7
RXIN
FIGURE 6 - INTERNAL BLOCK DIAGRAM