A0-A2

VALID

t1

nCS

t3

t5

nRD

t2

t4

t6

t7

D0-D7

VALID DATA

 

 

Parameter

min

max

units

t1

Address Setup to nRD Active

t2

Address Hold from nRD Inactive

t3

nCS Setup to nRD Active

t4

nCS Hold from nRD Inactive

t5

Cycle Time (nRD Low to Next Time Low)

t6

nRD Low to Valid Data

t7

nRD High to Data High Impedance

15nS

10nS

5**nS

0nS

4T*

 

nS

 

40

nS

0

20

nS

*T is the Arbitration Clock Period.

T is identical to XTAL1 if SLOW ARB = 0, T is twice XTAL1 period if SLOW ARB = 1

**nCS may become active after control becomes active, but the access time will now be 45nS measured from the leading edge of nCS.

Note 1: The Microcontroller typically accesses the COM20020 on every other cycle. Therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back COM20020 cycles.

FIGURE 12 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE

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SMSC COM20020 manual NON-MULTIPLEXED BUS, 80XX-LIKE Control Signals Read Cycle