CC2420
SWRS041B Page 48 of 89
21.8 Timing Table 8 shows some examples of the time
used by the security module for different
operations.
Mode l(a) l(m) l(MIC) Time
[us]
CCM 50 69 8 222
CTR - 15 - 99
CBC 17 98 12 99
Stand-
alone
- 16 - 14
Table 8. Security timing examples
CC2420
is based on a linear IF chain
where the signal amplification is done in
an analog VGA (variable gain amplifier).
The gain of the VGA is digitally controlled.
The AGC (Automatic Gain Control) loop
ensures that the ADC operates inside its
dynamic range by using an analog/digital
feedback loop.
The AGC characteristics are set through
the AGCCTRL, AGCTST0, AGCTST1 and
AGCTST2 registers. The reset values
should be used for all AGC control and
test registers.
23 RSSI / Energy Detection CC2420
has a built-in RSSI (Received
Signal Strength Indicator) providing a
digital value that can be read from the 8
bit, signed 2’s complement
RSSI.RSSI_VAL register.
The RSSI value is always averaged over 8
symbol periods (128 µs), in accordance
with [1]. The RSSI_VALID status bit
(Table 5) indicates when the RSSI value is
valid, meaning that the receiver has been
enabled for at least 8 symbol periods.
The RSSI register value RSSI.RSSI_VAL
can be referred to the power P at the RF
pins by using the following equations:
P = RSSI_VAL + RSSI_OFFSET [dBm]
where the RSSI_OFFSET is found
empirically during system development
from the front end gain. RSSI_OFFSET is
approximately –45. E.g. if reading a value
of –20 from the RSSI register, the RF
input power is approximately –65 dBm.
A typical plot of the RSSI_VAL reading as
function of input power is shown in Figure
27. It can be seen from the figure that the
RSSI reading from
CC2420
is very linear
and has a dynamic range of about 100 dB.
The RSSI register value RSSI.RSSI_VAL
is calculated and continuously updated for
each symbol after RSSI has become valid.