Digital Inputs/Outputs, Vdd | Texas Instruments 3138 155 232931

CC2420

Parameter

Min.

Typ.

Max.

Unit

Condition / Note

Crystal load capacitance

Crystal ESR

Crystal oscillator start-up time

Phase noise

PLL loop bandwidth

PLL lock time

12

16

1.0

−109 −117 −117 −117

100

20

60

192

pF

Ω

ms

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

kHz

∝s

16 pF recommended

16 pF load

Unmodulated carrier

At ±1 MHz offset from carrier At ±2 MHz offset from carrier At ±3 MHz offset from carrier At ±5 MHz offset from carrier

The startup time from the crystal oscillator is running and RX / TX turnaround time

6.7Digital Inputs/Outputs

Parameter	Min.	Typ.	Max.	Unit	Condition / Note
General					Signal levels are referred to the
					voltage level at pin DVDD3.3
Logic "0" input voltage	0		0.3*	V
			DVDD
Logic "1" input voltage	0.7*		DVDD	V
	DVDD
Logic "0" output voltage	0		0.4	V	Output current −8 mA,
					3.3 V supply voltage
Logic "1" output voltage	2.5		VDD	V	Output current 8 mA,
					3.3 V supply voltage
Logic "0" input current	NA		−1	∝A	Input signal equals GND
Logic "1" input current	NA		1	∝A	Input signal equals VDD
FIFO setup time	20			ns	TX unbuffered mode, minimum
					time FIFO must be ready before
					the positive edge of FIFOP
FIFO hold time	10			ns	TX unbuffered mode, minimum
					time FIFO must be held after the
					positive edge of FIFOP
Serial interface pins (SCLK, SI, SO					See Table 4 on page 28
and CSn) timing specification

		SWRS041B			Page 12 of 89

Image 12

Texas Instruments 3138 155 232931 manual Digital Inputs/Outputs, Vdd

Contents

Key Features ApplicationsProduct Description Table of contents RF Data Buffering Ordering Information General Information Abbreviations ITU-T References Features Absolute Maximum Ratings Operating ConditionsParameter Min Max Units Condition Parameter Min Typ Max Units Condition Electrical Specifications OverallTransmit Section Parameter Min Typ Max Unit Condition / Note Receive Section Rssi / Carrier Sense If SectionFrequency Synthesizer Section Digital Inputs/Outputs VDD Battery Monitor Power SupplyVoltage Regulator CC2420 Pin Assignment Pin Pin Name Pin type Pin Description Avddadc CC2420 simplified block diagram Circuit Description CC2420 Power supply decoupling and filtering Application CircuitInput / output matching Bias resistor Overview of external components Description Transceiver Transceiver Bill of materials for the application circuits Symbol Chip sequence C0, C1, C2, … , C31 Ieee 802.15.4 Modulation Format Configuration Overview Phase Evaluation Software SmartRF Studio user interface 13 4-wire Serial Configuration and Data Interface Pin configurationRegister access SPI timing specification Status byte Parameter Symbol Min Max Units Conditions RAM access Configuration registers write and read operations via SPI CC2420 RAM Memory Space Fifo access Multiple SPI accessAddress Byte Ordering Name Description Configuration interface Microcontroller Interface and Pin Description Receive mode Rxfifo overflow Pin activity examples during receive Demodulator, Symbol Synchroniser and Data Decision Demodulator Simplified Block Diagram Frame Format Transmitted Synchronisation Header Length field MAC protocol data unit Format of the Frame Control Field FCF Frame check sequence Buffered transmit mode Buffered receive modeRF Data Buffering Unbuffered, serial mode Fifop Address Recognition Acknowledge Frames Acknowledge frame format Radio control state machine Radio control states MAC Security Operations Encryption and Authentication KeysNonce / counter Ieee 802.15.4 Nonce CC2420 Security Flag Byte Stand-alone encryption In-line security operations CTR mode encryption / decryption CBC-MAC21.7 CCM Linear if and AGC Settings Mode LMIC TimeRssi / Energy Detection Timing Link Quality Indication ValueRF Level dBm Clear Channel Assessment Frequency and Channel Programming Output Power Programming VCO and PLL Self-CalibrationVoltage Regulator 27.1 VCO Battery Monitor Voltage regulator, simplified schematic Crystal Oscillator Input / Output Matching Transmitter Test ModesCrystal oscillator component values Unmodulated carrier CC2420 Modulated spectrum plot System Considerations and Guidelines Battery operated systems Low-cost systemsBER / PER measurements PCB Layout Recommendations Antenna Considerations CC2420 Configuration Registers Address Register Register type Description Configuration registers overview Saes Bit Field Name Reset Main 0x10 Main Control RegisterXOSC16MBYPASS MDMCTRL0 0x11 Modem Control Register Reservedframemode Pancoordinator AdrdecodeCCAHYST20 CCAMODE10 Autocrc Autoack Preamblelength MDMCTRL1 0x12- Modem Control Register Rssi 0x13 Rssi and CCA Status and Control RegisterCORRTHR40 Demodavgmode Modulationmode RSSIVAL70 Syncword 0x14 Sync Word Txctrl 0x15 Transmit Control Register RXCTRL0 0x16 Receive control register RXMIXBUFCUR10 RXCTRL1 0x17 Receive control register Fsctrl 0x18 Frequency Synthesizer Control and Status Caldone Calrunning Locklength Lockstatus SECCTRL0 0x19 Security Control Register SECMODE10 Battmon 0x1B Battery Monitor Control register SECCTRL1 0x1A Security Control RegisterSectxl Secrxl Battmonok Battmonen Battmonvoltage IOCFG0 0x1C I/O Configuration Register IOCFG1 0x1D I/O Configuration RegisterManfidl 0x1E Manufacturer ID, Lower 16 Bit HSSDSRC20 SFDMUX40 CCAMUX40 Manfidh 0x1F Manufacturer ID, Upper 16 Bit Fsmtc 0x20 Finite state machine time constants Manand 0x21 Manual signal and override register1 Isused = is * Isandmask + Isormask Manor 0x22 Manual signal or override register Agcctrl 0x23 AGC ControlVgagainoe Lnamixgainmodeo AGCTST0 0x24 AGC Test Register AGCTST1 0x25 AGC Test RegisterAGCTST2 0x26 AGC Test Register FSTST0 0x27 Frequency Synthesizer Test Register FSTST1 0x28 Frequency Synthesizer Test RegisterFSTST2 0x29 Frequency Synthesizer Test Register FSTST3 0x2A Frequency Synthesizer Test Register Rxbpftst 0x2B Receiver Bandpass Filters Test RegisterFsmstate 0x2C Finite state machine information Adcclockdisable Adctst 0x2D ADC Test RegisterDactst 0x2E DAC Test Register Oscillator must be running for accessing the Rxfifo Toptst 0x2F Top Level Test RegisterTxfifo 0x3E Transmit Fifo Byte register Rxfifo 0x3F Receive Fifo Byte register Test Output Signals CCA test signal select tableSignal output on CCA pin Description SFD test signal select table Signal output on SFD pin Description Package Description QLP Quad Leadless Package QLP Recommended layout for package QLP Package thermal propertiesSoldering information Thermal resistance 40.3 Plastic tube specification 40.4 Carrier tape and reel specificationTube Specification Tape and Reel Specification General Information 42.1 Document HistoryRevision Date Description/Changes Data Sheet Identification Product Status Definition Product Status Definitions Address Information TI Worldwide Technical Support InternetProduct Information Centers 2007, Texas Instruments. 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