CC2420

AGCTST0 (0x24) - AGC Test Register 0

 

 

 

 

 

 

 

Bit

Field Name

Reset

R/W

Description

15:12

LNAMIX_HYST[3:0]

3

R/W

Hysteresis on the switching between different RF front-end

 

 

 

 

gain modes, defined in 2 dB steps

11:6

LNAMIX_THR_H[5:0]

25

R/W

Threshold for switching between medium and high RF front-

 

 

 

 

end gain mode, defined in 2 dB steps

5:0

LNAMIX_THR_L[5:0]

9

R/W

Threshold for switching between low and medium RF front-end

 

 

 

 

gain mode, defined in 2 dB steps

AGCTST1 (0x25) - AGC Test Register 1

 

 

 

 

 

 

 

Bit

Field Name

Reset

R/W

Description

15

-

0

W0

Reserved, write as 0

14

AGC_BLANK_MODE

0

R/W

Set the VGA blanking mode when switching out a gain stage

 

 

 

 

When VGA_GAIN_OE = 0:

 

 

 

 

0 : Blanking is performed when the AGC algorithm switches

 

 

 

 

out one or more 14dB gain stages.

 

 

 

 

1 : Blanking is never performed.

 

 

 

 

When VGA_GAIN_OE = 1:

 

 

 

 

Blanking is performed when AGC_BLANK_MODE=1

13

PEAKDET_CUR_BOOST

0

R/W

Doubles the bias current in the peak-detectors in-between the

 

 

 

 

VGA stages when set.

12:11

AGC_SETTLE_WAIT[1:0]

1

R/W

Timing for AGC to wait for analog gain to settle.

10:8

AGC_PEAK_DET_MODE

0

R/W

Sets the AGC mode for use of the VGA peak detectors:

 

[2:0]

 

 

Bit 2 : Digital ADC peak detector enable / disable

 

 

 

 

Bit 1 : Analog fixed stages peak detector enable /

 

 

 

 

disable

 

 

 

 

Bit 0 : Analog variable gain stage peak detector enable /

 

 

 

 

disable

 

 

 

 

 

7:6

AGC_WIN_SIZE[1:0]

1

R/W

Window size for the accumulate and dump function in the

 

 

 

 

AGC.

 

 

 

 

0 : 8 samples

 

 

 

 

1 : 16 samples

 

 

 

 

2 : 32 samples

 

 

 

 

3 : 64 samples

 

 

 

 

 

5:0

AGC_REF[5:0]

20

R/W

Target value for the AGC control loop, given in 2 dB steps.

 

 

 

 

Reset value corresponds to approximately 25% of the ADC

 

 

 

 

dynamic range in reception.

 

 

 

 

 

AGCTST2 (0x26) - AGC Test Register 2

 

 

 

 

 

 

 

Bit

Field Name

Reset

R/W

Description

15:10

-

0

W0

Reserved, write as 0

9:5

MED2HIGHGAIN[4:0]

9

R/W

MED2HIGHGAIN sets the difference in the receiver

 

 

 

 

LNA/MIXER gain from medium gain mode to high gain mode,

 

 

 

 

used by the AGC for setting the correct front-end gain mode.

 

 

 

 

 

4:0

LOW2MEDGAIN[4:0]

10

R/W

LOW2MEDGAIN sets the difference in the receiver

 

 

 

 

LNA/MIXER gain from low gain mode to medium gain mode,

 

 

 

 

used by the AGC for setting the correct front-end gain mode.

 

 

 

 

 

SWRS041B

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Texas Instruments 3138 155 232931 manual AGCTST0 0x24 AGC Test Register, AGCTST1 0x25 AGC Test Register