Agcctrl 0x23 AGC Control | Texas Instruments 3138 155 232931

CC2420

MANOR (0x22) - Manual signal OR override register

Bit	Field Name	Reset	R/W
15	VGA_RESET_N	0	R/W

14	BIAS_PD	0	R/W
13	BALUN_CTRL	0	R/W

12	RXTX	0	R/W

11	PRE_PD	0	R/W
10	PA_N_PD	0	R/W
9	PA_P_PD	0	R/W

8	DAC_LPF_PD	0	R/W
7	XOSC16M_PD	0
6	RXBPF_CAL_PD	0	R/W

5	CHP_PD	0	R/W
4	FS_PD	0	R/W
3	ADC_PD	0	R/W
2	VGA_PD	0	R/W
1	RXBPF_PD	0	R/W
0	LNAMIX_PD	0	R/W

Description

The VGA_RESET_N signal is used to reset the peak detectors in the VGA in the RX chain.

Global Bias power down (1)

The BALUN_CTRL signal controls whether the PA should receive its required external biasing (1) or not (0) by controlling the RX/TX output switch.

RXTX signal: controls whether the LO buffers (0) or PA buffers

(1)should be used. Powerdown of prescaler. Powerdown of PA (negative path).

Powerdown of PA (positive path). When PA_N_PD=1 and PA_P_PD=1 the up-conversion mixers are in powerdown.

Powerdown of TX DACs.

Powerdown control of complex bandpass receive filter calibration oscillator.

Powerdown control of charge pump.

Powerdown control of VCO, I/Q generator, LO buffers.

Powerdown control of the ADCs.

Powerdown control of the VGA.

Powerdown control of complex bandpass receive filter.

Powerdown control of LNA, down-conversion mixers and front- end bias.

AGCCTRL (0x23) - AGC Control

	Bit	Field Name	Reset	R/W
	15:12	-	0	W0
	11	VGA_GAIN_OE	0	R/W
	10:4	VGA_GAIN [6:0]	0x7F	R/W

	3:2	LNAMIX_GAINMODE_O	0	R/W
		[1:0]

1:0	LNAMIX_GAINMODE	3	R
	[1:0]

Description

Reserved, write as 0

Use the VGA_GAIN value during RX instead of the AGC value.

When written, VGA manual gain override value; when read, the currently used VGA gain setting.

LNA / Mixer Gain mode override setting

0 : Gain mode is set by AGC algorithm

1 : Gain mode is always low-gain

2 : Gain mode is always med-gain

3 : Gain mode is always high-gain

Status bit, defining the currently selected gain mode selected by the AGC or overridden by the LNAMIX_GAINMODE_O setting.

SWRS041B

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Texas Instruments 3138 155 232931 manual Manor 0x22 Manual signal or override register, Agcctrl 0x23 AGC Control, Vgagainoe

Contents

Key Features ApplicationsProduct Description Table of contents RF Data Buffering Ordering Information General Information ITU-T Abbreviations References Features Parameter Min Typ Max Units Condition Absolute Maximum RatingsOperating Conditions Parameter Min Max Units Condition Parameter Min Typ Max Unit Condition / Note Electrical SpecificationsOverall Transmit Section Receive Section Rssi / Carrier Sense If SectionFrequency Synthesizer Section VDD Digital Inputs/Outputs Battery Monitor Power SupplyVoltage Regulator CC2420 Pin Pin Name Pin type Pin Description Pin Assignment Avddadc Circuit Description CC2420 simplified block diagram CC2420 Bias resistor Power supply decoupling and filteringApplication Circuit Input / output matching Description Overview of external components Transceiver Transceiver Bill of materials for the application circuits Ieee 802.15.4 Modulation Format Symbol Chip sequence C0, C1, C2, … , C31 Phase Configuration Overview SmartRF Studio user interface Evaluation Software 13 4-wire Serial Configuration and Data Interface Pin configurationRegister access Parameter Symbol Min Max Units Conditions SPI timing specification Status byte RAM access Configuration registers write and read operations via SPI CC2420 RAM Memory Space Fifo access Multiple SPI accessAddress Byte Ordering Name Description Microcontroller Interface and Pin Description Configuration interface Rxfifo overflow Receive mode Pin activity examples during receive Demodulator, Symbol Synchroniser and Data Decision Frame Format Demodulator Simplified Block Diagram MAC protocol data unit Transmitted Synchronisation Header Length field Format of the Frame Control Field FCF Frame check sequence Buffered transmit mode Buffered receive modeRF Data Buffering Fifop Unbuffered, serial mode Acknowledge Frames Address Recognition Acknowledge frame format Radio control state machine Radio control states Ieee 802.15.4 Nonce MAC Security Operations Encryption and AuthenticationKeys Nonce / counter In-line security operations CC2420 Security Flag Byte Stand-alone encryption CTR mode encryption / decryption CBC-MAC21.7 CCM Timing Linear if and AGC SettingsMode LMIC Time Rssi / Energy Detection Link Quality Indication ValueRF Level dBm Frequency and Channel Programming Clear Channel Assessment 27.1 VCO Output Power ProgrammingVCO and PLL Self-Calibration Voltage Regulator Voltage regulator, simplified schematic Battery Monitor Crystal Oscillator Unmodulated carrier Input / Output MatchingTransmitter Test Modes Crystal oscillator component values CC2420 Modulated spectrum plot System Considerations and Guidelines Battery operated systems Low-cost systemsBER / PER measurements Antenna Considerations PCB Layout Recommendations CC2420 Address Register Register type Description Configuration Registers Saes Configuration registers overview Bit Field Name Reset Main 0x10 Main Control RegisterXOSC16MBYPASS MDMCTRL0 0x11 Modem Control Register Reservedframemode Pancoordinator AdrdecodeCCAHYST20 CCAMODE10 Autocrc Autoack Preamblelength RSSIVAL70 MDMCTRL1 0x12- Modem Control RegisterRssi 0x13 Rssi and CCA Status and Control Register CORRTHR40 Demodavgmode Modulationmode Txctrl 0x15 Transmit Control Register Syncword 0x14 Sync Word RXMIXBUFCUR10 RXCTRL0 0x16 Receive control register RXCTRL1 0x17 Receive control register Caldone Calrunning Locklength Lockstatus Fsctrl 0x18 Frequency Synthesizer Control and Status SECMODE10 SECCTRL0 0x19 Security Control Register Battmonok Battmonen Battmonvoltage Battmon 0x1B Battery Monitor Control registerSECCTRL1 0x1A Security Control Register Sectxl Secrxl HSSDSRC20 SFDMUX40 CCAMUX40 IOCFG0 0x1C I/O Configuration RegisterIOCFG1 0x1D I/O Configuration Register Manfidl 0x1E Manufacturer ID, Lower 16 Bit Fsmtc 0x20 Finite state machine time constants Manfidh 0x1F Manufacturer ID, Upper 16 Bit Isused = is * Isandmask + Isormask Manand 0x21 Manual signal and override register1 Lnamixgainmodeo Manor 0x22 Manual signal or override registerAgcctrl 0x23 AGC Control Vgagainoe AGCTST0 0x24 AGC Test Register AGCTST1 0x25 AGC Test RegisterAGCTST2 0x26 AGC Test Register FSTST0 0x27 Frequency Synthesizer Test Register FSTST1 0x28 Frequency Synthesizer Test RegisterFSTST2 0x29 Frequency Synthesizer Test Register FSTST3 0x2A Frequency Synthesizer Test Register Rxbpftst 0x2B Receiver Bandpass Filters Test RegisterFsmstate 0x2C Finite state machine information Adcclockdisable Adctst 0x2D ADC Test RegisterDactst 0x2E DAC Test Register Rxfifo 0x3F Receive Fifo Byte register Oscillator must be running for accessing the RxfifoToptst 0x2F Top Level Test Register Txfifo 0x3E Transmit Fifo Byte register Test Output Signals CCA test signal select tableSignal output on CCA pin Description Signal output on SFD pin Description SFD test signal select table Quad Leadless Package QLP Package Description QLP Thermal resistance Recommended layout for package QLPPackage thermal properties Soldering information Tape and Reel Specification 40.3 Plastic tube specification40.4 Carrier tape and reel specification Tube Specification General Information 42.1 Document HistoryRevision Date Description/Changes Product Status Definitions Data Sheet Identification Product Status Definition Address Information TI Worldwide Technical Support InternetProduct Information Centers 2007, Texas Instruments. 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