Texas Instruments 3138 155 232931 39 Package Description (QLP 48)

CC2420

SWRS041B Page 83 of 89

39 Package Description (QLP 48)

Note: The figure is an illustration only and not to scale.

Quad Leadless Package (QLP)

D D1 E E1 e b L D2 E2

QLP 48 Min

Max

6.9

7.0

7.1

6.65

6.75

6.85

6.9

7.0

7.1

6.65

6.75

6.85

0.5

0.18

0.30

0.3

0.4

0.5

5.05

5.10

5.15

5.05

5.10

5.15

The overall packet height is 0.85 +/- 0.05

All dimensions in mm

The package is compliant to JEDEC standard MO-220.

Contents

Main 2.4 GHz IEEE 802.15.4 / ZigBee-ready RF Transceiver Applications Product Description Key Features Page Page 1 Abbreviations 2 References 3 Features 4 Absolute Maximum Ratings the limiting values may cause permanent damage to the device. 5 Operating Conditions 6 Electrical Specifications 6.1 Overall 6.2 Transmit Section 6.3 Receive Section 6.4 RSSI / Carrier Sense 6.5 IF Section 6.6 Frequency Synthesizer Section 6.7 Digital Inputs/Outputs 6.8 Voltage Regulator 6.9 Battery Monitor 6.10 Power Supply Page 7 Pin Assignment CC2420 Figure 1. QLP48 7x7 Pinout Top View Page 8 Circuit Description SmartRF Figure 2. ADC ADC CC2420 simplified block diagram Page 9 Application Circuit 9.1 Input / output matching 9.2 Bias resistor 9.3 Crystal 9.4 Voltage regulator R451 C42 C81 L81 L71 CC2420 RF Transceiver C391 C381 R451 C61 C71 CC2420 RF Transceiver Figure 5. Suggested application circuit with differential antenna (folded dipole) C391 C381 R451 Table 2. Bill of materials for the application circuits 10 IEEE 802.15.4 Modulation Format Figure 6. Modulation and spreading functions [1] Table 3. IEEE 802.15.4 symbol-to-chip mapping [1] Figure 7. I / Q Phases when transmitting a zero-symbol chip sequence, TC = 0.5 s 11 Configuration Overview 12 Evaluation Software Figure 8. SmartRF Studio user interface 13 4-wire Serial Configuration and Data Interface 13.1 Pin configuration 13.2 Register access Figure 9. SPI timing diagram Parameter Symbol Min Max Units Conditions SCLK, clock frequency F 13.3 Status byte Table 5. Status byte returned during address transfer and TXFIFO writing 13.4 Command strobes 13.5 RAM access Figure 10. Configuration registers write and read operations via SPI Table 6. RAM Memory Space 13.6 FIFO access 13.7 Multiple SPI access Figure 11. Multiple SPI Access Example 14 Microcontroller Interface and Pin Description Figure 12. Microcontroller interface example 14.1 Configuration interface 14.2 Receive mode 14.3 RXFIFO overflow Figure 13. Pin activity examples during receive Figure 14. Example of pin activity when reading RXFIFO. 14.4 Transmit mode Figure 15. Pin activity example during transmit 14.5 General control and status pins 15 Demodulator, Symbol Synchroniser and Data Decision Figure 16. Demodulator Simplified Block Diagram 16 Frame Format Figure 17. Schematic view of the IEEE 802.15.4 Frame Format [1] 16.1 Synchronisation header Figure 18. Transmitted Synchronisation Header 16.2 Length field 16.3 MAC protocol data unit Figure 19. Format of the Frame Control Field (FCF) [1] 16.4 Frame check sequence Figure 20. Frame Check Sequence (FCS) hardware implementation [1] Figure 21. Data in RXFIFO when MDMCTRL0.AUTOCRC is set 17 RF Data Buffering 17.1 Buffered transmit mode 17.2 Buffered receive mode 17.3 Unbuffered, serial mode Figure 22. Unbuffered test mode, pin activity 18 Address Recognition 19 Acknowledge Frames Figure 23. Acknowledge frame format [1] Figure 24. Acknowledge frame timing 20 Radio control state machine SWRS041B Page 44 of 89 Figure 25. Radio control states 21 MAC Security Operations (Encryption and Authentication) 21.1 Keys 21.2 Nonce / counter Table 7. IEEE 802.15.4 Nonce [1] Figure 26. Security Flag Byte 21.3 Stand-alone encryption 21.4 In-line security operations 21.5 CTR mode encryption / decryption 21.6 CBC-MAC 21.7 CCM 21.8 Timing Table 8. Security timing examples 22 Linear IF and AGC Settings 23 RSSI / Energy Detection Figure 27. Typical RSSI value vs. input power 24 Link Quality Indication 25 Clear Channel Assessment 26 Frequency and Channel Programming 27 VCO and PLL Self-Calibration 27.1 VCO 27.2 PLL self-calibration 28 Output Power Programming Table 9. Output power settings and typical current consumption @ 2.45 GHz 30 Battery Monitor Figure 29. Battery monitor, simplified schematic V 31 Crystal Oscillator CC C+ + = 32 Input / Output Matching 33 Transmitter Test Modes 33.1 Unmodulated carrier Figure 31. Single carrier output 33.2 Modulated spectrum Figure 32. Modulated spectrum plot SWRS041B Page 56 of 89 34 System Considerations and Guidelines SRD regulations 34.1 Frequency hopping and multi- channel systems 34.2 Data burst transmissions 34.3 Crystal accuracy and drift 34.6 Low-cost systems 34.7 Battery operated systems 34.8 BER / PER measurements 35 PCB Layout Recommendations 36 Antenna Considerations Page 37 Configuration Registers Table 11. Configuration registers overview MAIN (0x10) - Main Control Register MDMCTRL0 (0x11) - Modem Control Register 0 0), all frames are received and RESERVED_FRAME_MODE is dont 12 PAN_COORDINATOR 0 R/W Should be set high when the device is a PAN Coordinator. Used 11 ADR_DECODE 1 R/W Hardware Address decode enable. 10:8 CCA_HYST[2:0] 2 R/W 7:6 CCA_MODE[1:0] 3 R/W MDMCTRL1 (0x12) Modem Control Register 1 5 DEMOD_AVG_MODE 0 R/W 4 MODULATION_MODE 0 R/W 3:2 TX_MODE[1:0] 0 R/W 1:0 RX_MODE[1:0] 0 R/W SYNCWORD (0x14) - Sync Word 15:0 SYNCWORD[15:0] 0xA70F R/W Synchronisation word. The SYNCWORD is processed from the TXCTRL (0x15) - Transmit Control Register 15:14 TXMIXBUF_CUR[1:0] 2 R/W TX mixer buffer bias current. 13 TX_TURNAROUND 1 R/W Sets the wait time after STXON before transmission is started. RXCTRL0 (0x16) Receive control register 0 RXCTRL1 (0x17) - Receive control register 1 FSCTRL (0x18) - Frequency Synthesizer Control and Status SECCTRL0 (0x19) - Security Control Register 15:10 - 0 W0 9 RXFIFO_PROTECTION 1 R/W 8 SEC_CBC_HEAD 1 R/W 7 SEC_SAKEYSEL 1 R/W 6 SEC_TXKEYSEL 1 R/W V IOCFG0 (0x1C) I/O Configuration Register 0 15:12 - 0 W0 11 BCN_ACCEPT 0 R/W 10 FIFO_POLARITY 0 R/W 9 FIFOP_POLARITY 0 R/W 8 SFD_POLARITY 0 R/W MANFIDH (0x1F) - Manufacturer ID, Upper 16 Bit FSMTC (0x20) - Finite state machine time constants MANAND (0x21) - Manual signal AND override register1 MANOR (0x22) - Manual signal OR override register AGCCTRL (0x23) - AGC Control AGCTST0 (0x24) - AGC Test Register 0 AGCTST1 (0x25) - AGC Test Register 1 AGCTST2 (0x26) - AGC Test Register 2 FSTST0 (0x27) - Frequency Synthesizer Test Register 0 FSTST1 (0x28) - Frequency Synthesizer Test Register 1 FSTST2 (0x29) - Frequency Synthesizer Test Register 2 FSTST3 (0x2A) - Frequency Synthesizer Test Register 3 RXBPFTST (0x2B) - Receiver Bandpass Filters Test Register FSMSTATE (0x2C) - Finite state machine information ADCTST (0x2D) - ADC Test Register DACTST (0x2E) - DAC Test Register TOPTST (0x2F) - Top Level Test Register 15:8 - 0 W0 7 RAM_BIST_RUN 0 R/W Enable BIST of the RAM 4 ATESTMOD_PD 1 R/W Powerdown of analog test module. 3:0 ATESTMOD_MODE[3:0] 0 When ATESTMOD_PD=0, the function of the analog test module RESERVED (0x30) - Reserved register containing spare control and status bits 38 Test Output Signals IOCFG1.SFDMUX. This is summarized in Table 12 and Table 13 below. Table 12. CCA test signal select table Table 13. SFD test signal select table 39 Package Description (QLP 48) Note: The figure is an illustration only and not to scale. The package is compliant to JEDEC standard MO-220. 40 Recommended layout for package (QLP 48) 40.1 Package thermal properties 40.2 Soldering information 41 Ordering Information 42 General Information 42.1 Document History 42.2 Product Status Definitions 43 Address Information 44 TI Worldwide Technical Support Internet Product Information Centers 2007, Texas Instruments. All rights reserved. IMPORTANT NOTICE