Link Quality Indication, Value | Texas Instruments 3138 155 232931

CC2420

						60
Value						40
Value						20
Register						0
Register	-100	-80	-60	-40	-20	0
RSSI						-20
RSSI
						-40
						-60
			RF Level [dBm]

Figure 27. Typical RSSI value vs. input power

24 Link Quality Indication

The link quality indication (LQI) measurement is a characterisation of the strength and/or quality of a received packet, as defined by [1].

The RSSI value described in the previous section may be used by the MAC software to produce the LQI value. The LQI value is required by [1] to be limited to the range 0 through 255, with at least 8 unique values. Software is responsible for generating the appropriate scaling of the LQI value for the given application.

Using the RSSI value directly to calculate the LQI value has the disadvantage that e.g. a narrowband interferer inside the channel bandwidth will increase the LQI value although it actually reduces the true link quality. CC2420 therefore also provides an average correlation value for each incoming packet, based on the 8 first symbols following the SFD. This unsigned 7-bit value can be looked upon as a measurement of the “chip error rate,” although CC2420 does not do chip decision.

As described in the Frame check sequence section on page 38, the average correlation value for the 8 first symbols is appended to each received frame together with the RSSI and CRC OK/not OK when MDMCTRL0.AUTOCRC is set. A correlation value of ~110 indicates a maximum quality frame while a value of ~50 is typically the lowest quality frames detectable by

CC2420.

Software must convert the correlation value to the range 0-255 defined by [1], e.g. by calculating:

LQI = (CORR – a) · b

limited to the range 0-255, where a and b are found empirically based on PER measurements as a function of the correlation value.

A combination of RSSI and correlation values may also be used to generate the LQI value.

SWRS041B

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Texas Instruments 3138 155 232931 manual Link Quality Indication, Value, RF Level dBm

Contents

Applications Key FeaturesProduct Description Table of contents RF Data Buffering Ordering Information General Information ITU-T Abbreviations References Features Operating Conditions Absolute Maximum RatingsParameter Min Max Units Condition Parameter Min Typ Max Units Condition Overall Electrical SpecificationsTransmit Section Parameter Min Typ Max Unit Condition / Note Receive Section If Section Rssi / Carrier SenseFrequency Synthesizer Section VDD Digital Inputs/Outputs Power Supply Battery MonitorVoltage Regulator CC2420 Pin Pin Name Pin type Pin Description Pin Assignment Avddadc Circuit Description CC2420 simplified block diagram CC2420 Application Circuit Power supply decoupling and filteringInput / output matching Bias resistor Description Overview of external components Transceiver Transceiver Bill of materials for the application circuits Ieee 802.15.4 Modulation Format Symbol Chip sequence C0, C1, C2, … , C31 Phase Configuration Overview SmartRF Studio user interface Evaluation Software Pin configuration 13 4-wire Serial Configuration and Data InterfaceRegister access Parameter Symbol Min Max Units Conditions SPI timing specification Status byte RAM access Configuration registers write and read operations via SPI Multiple SPI access CC2420 RAM Memory Space Fifo accessAddress Byte Ordering Name Description Microcontroller Interface and Pin Description Configuration interface Rxfifo overflow Receive mode Pin activity examples during receive Demodulator, Symbol Synchroniser and Data Decision Frame Format Demodulator Simplified Block Diagram MAC protocol data unit Transmitted Synchronisation Header Length field Format of the Frame Control Field FCF Frame check sequence Buffered receive mode Buffered transmit modeRF Data Buffering Fifop Unbuffered, serial mode Acknowledge Frames Address Recognition Acknowledge frame format Radio control state machine Radio control states Keys MAC Security Operations Encryption and AuthenticationNonce / counter Ieee 802.15.4 Nonce In-line security operations CC2420 Security Flag Byte Stand-alone encryption CBC-MAC CTR mode encryption / decryption21.7 CCM Mode LMIC Time Linear if and AGC SettingsRssi / Energy Detection Timing Value Link Quality IndicationRF Level dBm Frequency and Channel Programming Clear Channel Assessment VCO and PLL Self-Calibration Output Power ProgrammingVoltage Regulator 27.1 VCO Voltage regulator, simplified schematic Battery Monitor Crystal Oscillator Transmitter Test Modes Input / Output MatchingCrystal oscillator component values Unmodulated carrier CC2420 Modulated spectrum plot System Considerations and Guidelines Low-cost systems Battery operated systemsBER / PER measurements Antenna Considerations PCB Layout Recommendations CC2420 Address Register Register type Description Configuration Registers Saes Configuration registers overview Main 0x10 Main Control Register Bit Field Name ResetXOSC16MBYPASS Reservedframemode Pancoordinator Adrdecode MDMCTRL0 0x11 Modem Control RegisterCCAHYST20 CCAMODE10 Autocrc Autoack Preamblelength Rssi 0x13 Rssi and CCA Status and Control Register MDMCTRL1 0x12- Modem Control RegisterCORRTHR40 Demodavgmode Modulationmode RSSIVAL70 Txctrl 0x15 Transmit Control Register Syncword 0x14 Sync Word RXMIXBUFCUR10 RXCTRL0 0x16 Receive control register RXCTRL1 0x17 Receive control register Caldone Calrunning Locklength Lockstatus Fsctrl 0x18 Frequency Synthesizer Control and Status SECMODE10 SECCTRL0 0x19 Security Control Register SECCTRL1 0x1A Security Control Register Battmon 0x1B Battery Monitor Control registerSectxl Secrxl Battmonok Battmonen Battmonvoltage IOCFG1 0x1D I/O Configuration Register IOCFG0 0x1C I/O Configuration RegisterManfidl 0x1E Manufacturer ID, Lower 16 Bit HSSDSRC20 SFDMUX40 CCAMUX40 Fsmtc 0x20 Finite state machine time constants Manfidh 0x1F Manufacturer ID, Upper 16 Bit Isused = is * Isandmask + Isormask Manand 0x21 Manual signal and override register1 Agcctrl 0x23 AGC Control Manor 0x22 Manual signal or override registerVgagainoe Lnamixgainmodeo AGCTST1 0x25 AGC Test Register AGCTST0 0x24 AGC Test RegisterAGCTST2 0x26 AGC Test Register FSTST1 0x28 Frequency Synthesizer Test Register FSTST0 0x27 Frequency Synthesizer Test RegisterFSTST2 0x29 Frequency Synthesizer Test Register Rxbpftst 0x2B Receiver Bandpass Filters Test Register FSTST3 0x2A Frequency Synthesizer Test RegisterFsmstate 0x2C Finite state machine information Adctst 0x2D ADC Test Register AdcclockdisableDactst 0x2E DAC Test Register Toptst 0x2F Top Level Test Register Oscillator must be running for accessing the RxfifoTxfifo 0x3E Transmit Fifo Byte register Rxfifo 0x3F Receive Fifo Byte register CCA test signal select table Test Output SignalsSignal output on CCA pin Description Signal output on SFD pin Description SFD test signal select table Quad Leadless Package QLP Package Description QLP Package thermal properties Recommended layout for package QLPSoldering information Thermal resistance 40.4 Carrier tape and reel specification 40.3 Plastic tube specificationTube Specification Tape and Reel Specification 42.1 Document History General InformationRevision Date Description/Changes Product Status Definitions Data Sheet Identification Product Status Definition TI Worldwide Technical Support Internet Address InformationProduct Information Centers 2007, Texas Instruments. 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