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| CC2420 |
42 | General Information | ||
42.1 | Document History | ||
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Revision | Date | Description/Changes | |
SWRS041b | |||
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| Application circuit. |
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SWRS041a | Updated ordering information. | ||
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| Updated address information. |
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| Typical data latency changed from 2 to 3 us. |
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| Updates reflecting the programmable polarity of FIFO, FIFOP, SFD and CCA pins. |
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| Clarification relating to VREG_EN as digital input. |
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| BATT_OK changed to BATTMON_OK for consistency. |
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| MANFIDH.VERSION register, reset value changed to ”current version is 3”. |
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| Added reset values for several registers. |
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| Some typographical changes. |
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| Removed Chipcon specific Disclaimer, Trademarks and Life Support Policy sections. |
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SWRS041 | |||
(1.4) |
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| RTB1 and |
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1.3
Updated address information.
Added new balun circuit with transmission lines in section Application Circuit. Updated electrical specifications with measured data on CC2420 EM with new balun. Updated values and figure for suggested application circuit with folded dipole antenna.
Corrected values for capacitors in Table 2, discrete balun. Added data latency figure in receiver specification. Updated crystal oscillator start up time.
Updated PLL loop filter bandwidth. Updated adjacent channel rejection figures. Updated current consumption for RX mode. Typographical errors corrected in text and figures.
Removed comment about tuning capacitor for crystal oscillator. Added statement that RAM access shall not be used for FIFO access. Added more details about RSSI.
Clarified the interpretation of a programmed synchronisation word. Updated purchasing information.
Updated soldering standard.
Added chapter numbering and split table for electrical specifications for readability. Gathered and added information related to pin configurations in section 13. Included TX_UNDERFLOW and RX_UNDERFLOW in state diagram.
Disclaimer updated to include
SWRS041B | Page 86 of 89 |
