Configuration interface | Texas Instruments 3138 155 232931 specification

CC2420

CSn

SI	ADDR	ADDR	-	-	ADDRTXFIFO	DATAADDR DATAADDR+1 DATAADDR+2
SO	Status	Status	DATA8MSB	DATA8LSB	Status	Status	Status	Status
	Command		Register			TXFIFO
	Strobe		Read			Write

Figure 11. Multiple SPI Access Example

14 Microcontroller Interface and Pin Description

When used in a typical system, CC2420 will interface to a microcontroller. This microcontroller must be able to:

•Program CC2420 into different modes, read and write buffered data, and read back status information via the 4-wire SPI-bus configuration interface (SI, SO,

SCLK and CSn).

•Interface to the receive and transmit FIFOs using the FIFO and FIFOP status pins.

•Interface to the CCA pin for clear channel assessment.

•Interface to the SFD pin for timing information (particularly for beaconing networks).

14.1 Configuration interface

A CC2420 to microcontroller interface example is shown in Figure 12. The microcontroller uses 4 I/O pins for the SPI

configuration interface (SI, SO, SCLK and CSn). SO should be connected to an input at the microcontroller. SI, SCLK and CSn must be microcontroller outputs. Preferably the microcontroller should have a hardware SPI interface.

The microcontroller pins connected to SI, SO and SCLK can be shared with other SPI-interface devices. SO is a high impedance output as long as CSn is not activated (active low).

CSn should have an external pull-up resistor or be set to a high level when the voltage regulator is turned off in order to prevent the input from floating. SI and SCLK should be set to a defined level to prevent the inputs from floating.

CC2420

FIFO

FIFOP

CCA

SFD

CSn

SI

SO

SCLK

∝C

GIO0

Interrupt

GIO1

Timer Capture

GIO2

MOSI

MISO

SCLK

Figure 12. Microcontroller interface example

SWRS041B

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Texas Instruments 3138 155 232931 manual Microcontroller Interface and Pin Description, Configuration interface

Contents

Product Description Key FeaturesApplications Table of contents RF Data Buffering Ordering Information General Information Abbreviations ITU-T References Features Absolute Maximum Ratings Operating ConditionsParameter Min Max Units Condition Parameter Min Typ Max Units Condition Electrical Specifications OverallTransmit Section Parameter Min Typ Max Unit Condition / Note Receive Section Frequency Synthesizer Section Rssi / Carrier SenseIf Section Digital Inputs/Outputs VDD Voltage Regulator Battery MonitorPower Supply CC2420 Pin Assignment Pin Pin Name Pin type Pin Description Avddadc CC2420 simplified block diagram Circuit Description CC2420 Power supply decoupling and filtering Application CircuitInput / output matching Bias resistor Overview of external components Description Transceiver Transceiver Bill of materials for the application circuits Symbol Chip sequence C0, C1, C2, … , C31 Ieee 802.15.4 Modulation Format Configuration Overview Phase Evaluation Software SmartRF Studio user interface Register access 13 4-wire Serial Configuration and Data InterfacePin configuration SPI timing specification Status byte Parameter Symbol Min Max Units Conditions RAM access Configuration registers write and read operations via SPI Address Byte Ordering Name Description CC2420 RAM Memory Space Fifo accessMultiple SPI access Configuration interface Microcontroller Interface and Pin Description Receive mode Rxfifo overflow Pin activity examples during receive Demodulator, Symbol Synchroniser and Data Decision Demodulator Simplified Block Diagram Frame Format Transmitted Synchronisation Header Length field MAC protocol data unit Format of the Frame Control Field FCF Frame check sequence RF Data Buffering Buffered transmit modeBuffered receive mode Unbuffered, serial mode Fifop Address Recognition Acknowledge Frames Acknowledge frame format Radio control state machine Radio control states MAC Security Operations Encryption and Authentication KeysNonce / counter Ieee 802.15.4 Nonce CC2420 Security Flag Byte Stand-alone encryption In-line security operations 21.7 CCM CTR mode encryption / decryptionCBC-MAC Linear if and AGC Settings Mode LMIC TimeRssi / Energy Detection Timing RF Level dBm Link Quality IndicationValue Clear Channel Assessment Frequency and Channel Programming Output Power Programming VCO and PLL Self-CalibrationVoltage Regulator 27.1 VCO Battery Monitor Voltage regulator, simplified schematic Crystal Oscillator Input / Output Matching Transmitter Test ModesCrystal oscillator component values Unmodulated carrier CC2420 Modulated spectrum plot System Considerations and Guidelines BER / PER measurements Battery operated systemsLow-cost systems PCB Layout Recommendations Antenna Considerations CC2420 Configuration Registers Address Register Register type Description Configuration registers overview Saes XOSC16MBYPASS Bit Field Name ResetMain 0x10 Main Control Register CCAHYST20 CCAMODE10 Autocrc Autoack Preamblelength MDMCTRL0 0x11 Modem Control RegisterReservedframemode Pancoordinator Adrdecode MDMCTRL1 0x12- Modem Control Register Rssi 0x13 Rssi and CCA Status and Control RegisterCORRTHR40 Demodavgmode Modulationmode RSSIVAL70 Syncword 0x14 Sync Word Txctrl 0x15 Transmit Control Register RXCTRL0 0x16 Receive control register RXMIXBUFCUR10 RXCTRL1 0x17 Receive control register Fsctrl 0x18 Frequency Synthesizer Control and Status Caldone Calrunning Locklength Lockstatus SECCTRL0 0x19 Security Control Register SECMODE10 Battmon 0x1B Battery Monitor Control register SECCTRL1 0x1A Security Control RegisterSectxl Secrxl Battmonok Battmonen Battmonvoltage IOCFG0 0x1C I/O Configuration Register IOCFG1 0x1D I/O Configuration RegisterManfidl 0x1E Manufacturer ID, Lower 16 Bit HSSDSRC20 SFDMUX40 CCAMUX40 Manfidh 0x1F Manufacturer ID, Upper 16 Bit Fsmtc 0x20 Finite state machine time constants Manand 0x21 Manual signal and override register1 Isused = is * Isandmask + Isormask Manor 0x22 Manual signal or override register Agcctrl 0x23 AGC ControlVgagainoe Lnamixgainmodeo AGCTST2 0x26 AGC Test Register AGCTST0 0x24 AGC Test RegisterAGCTST1 0x25 AGC Test Register FSTST2 0x29 Frequency Synthesizer Test Register FSTST0 0x27 Frequency Synthesizer Test RegisterFSTST1 0x28 Frequency Synthesizer Test Register Fsmstate 0x2C Finite state machine information FSTST3 0x2A Frequency Synthesizer Test RegisterRxbpftst 0x2B Receiver Bandpass Filters Test Register Dactst 0x2E DAC Test Register AdcclockdisableAdctst 0x2D ADC Test Register Oscillator must be running for accessing the Rxfifo Toptst 0x2F Top Level Test RegisterTxfifo 0x3E Transmit Fifo Byte register Rxfifo 0x3F Receive Fifo Byte register Signal output on CCA pin Description Test Output SignalsCCA test signal select table SFD test signal select table Signal output on SFD pin Description Package Description QLP Quad Leadless Package QLP Recommended layout for package QLP Package thermal propertiesSoldering information Thermal resistance 40.3 Plastic tube specification 40.4 Carrier tape and reel specificationTube Specification Tape and Reel Specification Revision Date Description/Changes General Information42.1 Document History Data Sheet Identification Product Status Definition Product Status Definitions Product Information Centers Address InformationTI Worldwide Technical Support Internet 2007, Texas Instruments. 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