Adctst 0x2D ADC Test Register | Texas Instruments 3138 155 232931

ADCTST (0x2D) - ADC Test Register

	Bit		Field Name		Reset		R/W
	15		ADC_CLOCK_DISABLE		0		R/W

	14:8		ADC_I[6:0]		0		R
	7		-		0		W0
	6:0		ADC_Q[6:0]		0		R
	DACTST (0x2E) - DAC Test Register

	Bit		Field Name		Reset		R/W

	15	-		0			W0
	14:12		DAC_SRC[2:0]	0			R/W

11:6	DAC_I_O[5:0]	0	R/W
5:0	DAC_Q_O[5:0]	0	R/W

CC2420

Description

ADC Clock Disable

0 : Clock enabled when ADC enabled

1 : Clock disabled, even if ADC is enabled

Read the current ADC I-branch value.

Reserved, write as 0.

Read the current ADC Q-branch value.

Description

Reserved, write as 0.

The TX DACs data source is selected by DAC_SRC according to:

0:Normal operation (from modulator).

1:The DAC_I_O and DAC_Q_O override values below.-

2:From ADC, most significant bits

3:I/Q after digital down mixing and channel filtering.

4:Full-spectrum White Noise (from CRC)

5:From ADC, least significant bits

6:RSSI / Cordic Magnitude Output

7:HSSD module.

This feature will often require the DACs to be manually turned on in MANOR and TOPTST.ATESTMOD_MODE=4.

I-branch DAC override value.

Q-branch DAC override value.

SWRS041B

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Texas Instruments 3138 155 232931 manual Adctst 0x2D ADC Test Register, Dactst 0x2E DAC Test Register, Adcclockdisable

Contents

Applications Key FeaturesProduct Description Table of contents RF Data Buffering Ordering Information General Information ITU-T Abbreviations References Features Parameter Min Typ Max Units Condition Absolute Maximum RatingsOperating Conditions Parameter Min Max Units Condition Parameter Min Typ Max Unit Condition / Note Electrical SpecificationsOverall Transmit Section Receive Section If Section Rssi / Carrier SenseFrequency Synthesizer Section VDD Digital Inputs/Outputs Power Supply Battery MonitorVoltage Regulator CC2420 Pin Pin Name Pin type Pin Description Pin Assignment Avddadc Circuit Description CC2420 simplified block diagram CC2420 Bias resistor Power supply decoupling and filteringApplication Circuit Input / output matching Description Overview of external components Transceiver Transceiver Bill of materials for the application circuits Ieee 802.15.4 Modulation Format Symbol Chip sequence C0, C1, C2, … , C31 Phase Configuration Overview SmartRF Studio user interface Evaluation Software Pin configuration 13 4-wire Serial Configuration and Data InterfaceRegister access Parameter Symbol Min Max Units Conditions SPI timing specification Status byte RAM access Configuration registers write and read operations via SPI Multiple SPI access CC2420 RAM Memory Space Fifo accessAddress Byte Ordering Name Description Microcontroller Interface and Pin Description Configuration interface Rxfifo overflow Receive mode Pin activity examples during receive Demodulator, Symbol Synchroniser and Data Decision Frame Format Demodulator Simplified Block Diagram MAC protocol data unit Transmitted Synchronisation Header Length field Format of the Frame Control Field FCF Frame check sequence Buffered receive mode Buffered transmit modeRF Data Buffering Fifop Unbuffered, serial mode Acknowledge Frames Address Recognition Acknowledge frame format Radio control state machine Radio control states Ieee 802.15.4 Nonce MAC Security Operations Encryption and AuthenticationKeys Nonce / counter In-line security operations CC2420 Security Flag Byte Stand-alone encryption CBC-MAC CTR mode encryption / decryption21.7 CCM Timing Linear if and AGC SettingsMode LMIC Time Rssi / Energy Detection Value Link Quality IndicationRF Level dBm Frequency and Channel Programming Clear Channel Assessment 27.1 VCO Output Power ProgrammingVCO and PLL Self-Calibration Voltage Regulator Voltage regulator, simplified schematic Battery Monitor Crystal Oscillator Unmodulated carrier Input / Output MatchingTransmitter Test Modes Crystal oscillator component values CC2420 Modulated spectrum plot System Considerations and Guidelines Low-cost systems Battery operated systemsBER / PER measurements Antenna Considerations PCB Layout Recommendations CC2420 Address Register Register type Description Configuration Registers Saes Configuration registers overview Main 0x10 Main Control Register Bit Field Name ResetXOSC16MBYPASS Reservedframemode Pancoordinator Adrdecode MDMCTRL0 0x11 Modem Control RegisterCCAHYST20 CCAMODE10 Autocrc Autoack Preamblelength RSSIVAL70 MDMCTRL1 0x12- Modem Control RegisterRssi 0x13 Rssi and CCA Status and Control Register CORRTHR40 Demodavgmode Modulationmode Txctrl 0x15 Transmit Control Register Syncword 0x14 Sync Word RXMIXBUFCUR10 RXCTRL0 0x16 Receive control register RXCTRL1 0x17 Receive control register Caldone Calrunning Locklength Lockstatus Fsctrl 0x18 Frequency Synthesizer Control and Status SECMODE10 SECCTRL0 0x19 Security Control Register Battmonok Battmonen Battmonvoltage Battmon 0x1B Battery Monitor Control registerSECCTRL1 0x1A Security Control Register Sectxl Secrxl HSSDSRC20 SFDMUX40 CCAMUX40 IOCFG0 0x1C I/O Configuration RegisterIOCFG1 0x1D I/O Configuration Register Manfidl 0x1E Manufacturer ID, Lower 16 Bit Fsmtc 0x20 Finite state machine time constants Manfidh 0x1F Manufacturer ID, Upper 16 Bit Isused = is * Isandmask + Isormask Manand 0x21 Manual signal and override register1 Lnamixgainmodeo Manor 0x22 Manual signal or override registerAgcctrl 0x23 AGC Control Vgagainoe AGCTST1 0x25 AGC Test Register AGCTST0 0x24 AGC Test RegisterAGCTST2 0x26 AGC Test Register FSTST1 0x28 Frequency Synthesizer Test Register FSTST0 0x27 Frequency Synthesizer Test RegisterFSTST2 0x29 Frequency Synthesizer Test Register Rxbpftst 0x2B Receiver Bandpass Filters Test Register FSTST3 0x2A Frequency Synthesizer Test RegisterFsmstate 0x2C Finite state machine information Adctst 0x2D ADC Test Register AdcclockdisableDactst 0x2E DAC Test Register Rxfifo 0x3F Receive Fifo Byte register Oscillator must be running for accessing the RxfifoToptst 0x2F Top Level Test Register Txfifo 0x3E Transmit Fifo Byte register CCA test signal select table Test Output SignalsSignal output on CCA pin Description Signal output on SFD pin Description SFD test signal select table Quad Leadless Package QLP Package Description QLP Thermal resistance Recommended layout for package QLPPackage thermal properties Soldering information Tape and Reel Specification 40.3 Plastic tube specification40.4 Carrier tape and reel specification Tube Specification 42.1 Document History General InformationRevision Date Description/Changes Product Status Definitions Data Sheet Identification Product Status Definition TI Worldwide Technical Support Internet Address InformationProduct Information Centers 2007, Texas Instruments. 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