Appendices

Apx. C Pin Assignments

175

/M_DATA(51)'

I/O

176

177

DGND'

-

178

179

/M_DATA(56)'

I/O

180

181

/M_DATA(57)'

I/O

182

183

DGND'

-

184

185

/M_DM(7)'

-

186

187

DGND'

-

188

189

/M_DATA(58)'

I/O

190

191

/M_DATA(59)'

I/O

192

193

DGND'

-

194

195

/SB_SMDAT_3'

I/O

196

197

/SB_SMCLK_3'

I/O

198

199

/+V3S'

-

200

/M_DATA(55)'

DGND'

/M_DATA(60)' /M_DATA(61)' DGND' /M_DQS#(7)' /M_DQS(7)' DGND' /M_DATA(62)' /M_DATA(63)' DGND' /N$837418' /N$837419'

I/O

-

I/O

I/O

O

I/O

I/O

-

I/O

I/O

-

-

-

C.33 CN508 DDR2 DIMM1 Socket (200-Pin)

Table C-33 DDR2 DIMM1 Socket pin assignments (200-Pin)

 

Pin No.

 

Signal Name

I/O

Pin No.

 

 

 

 

 

 

 

 

 

1

 

/SM_VREF'

I/O

2

 

 

3

 

DGND'

-

4

 

 

5

 

/M_DATA(0)'

I/O

6

 

 

7

 

/M_DATA(1)'

I/O

8

 

 

9

 

DGND'

-

10

 

 

11

 

/M_DQS#(0)'

O

12

 

 

13

 

/M_DQS(0)'

I/O

14

 

 

15

 

DGND'

-

16

 

 

17

 

/M_DATA(2)'

I/O

18

 

 

19

 

/M_DATA(3)'

I/O

20

 

 

21

 

DGND'

-

22

 

 

23

 

/M_DATA(8)'

I/O

24

 

 

25

 

/M_DATA(9)'

O

26

 

 

27

 

DGND'

-

28

 

 

29

 

/M_DQS#(1)'

I/O

30

 

 

31

 

/M_DQS(1)'

I/O

32

 

 

33

 

DGND'

-

34

 

 

 

 

 

Signal Name

DGND'

/M_DATA(4)' /M_DATA(5)' DGND' /M_DM(0)' DGND' /M_DATA(6)' /M_DATA(7)' DGND' /M_DATA(12)' /M_DATA(13)' DGND' /M_DM(1)' DGND' /M_CLK_DDR1' /M_CLK_DDR1#'

DGND'

I/O

-

I

I/O-

-

-

-

I/O

-

I/O

I/O

I/O

-

O

-

I/O

I/O

-

C-26

Satellite A100/A105 / TECRA A7 Maintenance Manual

Page 261
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Toshiba PTA71, PTA70, PSAA9 manual 33 CN508 DDR2 DIMM1 Socket 200-Pin, Table C-33 DDR2 DIMM1 Socket pin assignments 200-Pin