Memory Mapped Addressing | Transcend Information TS32M~1GCF80

TS32M~1GCF80		80X CompactFlash Card

5.3 Memory Mapped Addressing

When the CompactFlash Storage Card registers are accessed via memory references, the registers appear in the common memory space window: 0-2K bytes as follows:

Notes:

1)Register 0 is accessed with -CE1 low and -CE2 low as a word register on the combined Odd Data Bus and Even Data Bus (D15-D0). This register may also be accessed by a pair of byte accesses to the offset 0 with -CE1 low and -CE2 high. Note that the address space of this word register overlaps the address space of the Error and Feature byte-wide registers that lie at offset 1. When accessed twice as byte register with -CE1 low, the first byte to be accessed is the even byte of the word and the second byte accessed is the odd byte of the equivalent word access.

A byte access to address 0 with -CE1 high and -CE2 low accesses the error (read) or feature (write) register.

2)Registers at offset 8, 9 and D are non-overlapping duplicates of the registers at offset 0 and 1.Register 8 is equivalent to register 0, while register 9 accesses the odd byte. Therefore, if the registers are byte accessed in the order 9 then 8 the data shall be transferred odd byte then even byte.

Repeated byte accesses to register 8 or 0 shall access consecutive (even then odd) bytes from the data buffer. Repeated word accesses to register 8, 9 or 0 shall access consecutive words from the data buffer. Repeated byte accesses to register 9 are not supported. However, repeated alternating byte accesses to registers 8 then 9 shall access consecutive (even then odd) bytes from the data buffer. Byte accesses to register 9 access only the odd byte of the data.

3)Accesses to even addresses between 400h and 7FFh access register 8. Accesses to odd addresses between 400h and 7FFh access register 9. This 1 Kbyte memory window to the data register is provided so that hosts can perform memory to memory block moves to the data register when the register lies in memory space.

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Transcend Information TS32M~1GCF80 dimensions Memory Mapped Addressing

Contents

Description Placement FeatureDimensions 80X CompactFlash Card Ordering Information CHS and Capacity Compactflash Card Specification Block Diagram PC Card Memory Mode PC Card I/O Mode True IDE Mode4 Electrical Interface Pin Assignment and Pin Type V1.1 Signal Description Signal Name Dir Pin Description Csel V1.1 Iord REG True IDE Mode As Iordy Electrical Specification Input Leakage Current Input Characteristics CompactFlash interface I/O at Parameter Symbol Min Max Unit Remark Parameter Min Max Unit Output Drive Type Output Drive Characteristics Signal Interface Signal Card Host TS32M~1GCF8080X CompactFlash Card 150 μ a high state per socket Figure Attribute Memory Read Timing Diagram Attribute Memory Read Timing Configuration Register Attribute Memory Write Timing Min Max Symbol Common Memory Read Timing SpecificationCycle Time Mode 250 ns 120 ns 100 ns 80 ns Common Memory Write Timing Specification Min Symbol I/O Input Read Timing Specification 80X CompactFlash Card 10 I/O Output Write Timing Specification Cycle Time Mode 255 ns 120 ns 100 ns 80 ns True IDE PIO Mode Read/Write Timing Specification Mode V1.1 True IDE Multiword DMA Mode Read/Write Timing Specification CE2 CE1 Card ConfigurationMultiple Function CompactFlash Storage Cards A10 A8-A4 CE2 CE1 A10 D15-D8 D7-D0 Function ModeAttribute Memory Function Table CompactFlash Storage Card Configurations Configuration Option RegisterBase + 00h in Attribute Memory Pin Replacement Register Base + 04h in Attribute Memory Table Pin Replacement Changed Bit/Mask Bit Values Socket and Copy Register Base + 06h in Attribute Memory I/O Transfer Function Common Memory Transfer Function True IDE Mode I/O Transfer FunctionTable Pcmcia Mode I/O Function Function Code V1.1 Table I/O Configurations CF-ATA Drive Register Set Definition and Protocol I/O Primary and Secondary Address Configurations Table Primary and Secondary I/O Decoding Contiguous I/O Mapped Addressing Table Contiguous I/O Decoding Memory Mapped Addressing Data Register Address 1F0h170hOffset 0,8,9 True IDE Mode AddressingCF-ATA Registers Error Register Address 1F1h171h Offset 1, 0Dh Read Only Table Data Register Access Sector Number LBA 7-0 Register Address 1F3h173h Offset Feature Register Address 1F1h171h Offset 1, 0Dh Write OnlySector Count Register Address 1F2h172h Offset Cylinder Low LBA 15-8 Register Address 1F4h174h Offset Device Control Register Address 3F6h376h Offset Eh Figure Status & Alternate Status Register Card Drive Address Register Address 3F7h377h Offset Fh Figure Device Control Register CF-ATA Command Description CF-ATA Command Set LBA Definitions Bit Command Check Power Mode 98h or E5hExecute Drive Diagnostic 90h Cyl High Cyl Low Sec Num Sec Cnt Feature Drive Head LBA Cyl High Erase Sectors C0hFormat Track 50h Sec Num LBA Sec Cnt Bytes Word Default Total Data Field Type InformationIdentify Device Ech Total Data Field Type Information Word 3 Default Number of Heads Word 0 General ConfigurationWord 1 Default Number of Cylinders Word 6 Default Number of Sectors per Track Multiple Sector Setting Word 49 Capabilities Bit 13 Standby TimerPIO Data Transfer Cycle Timing Mode Total Sectors Addressable in LBA Mode Word 65 Minimum Multiword DMA transfer cycle time Multiword DMA transferWord 64 Advanced PIO transfer modes supported Recommended Multiword DMA transfer cycle time Word 68 Minimum PIO transfer cycle time with Iordy Words 82-84 Features/command sets supportedWords 85-87 Features/command sets enabled Word 128 Security Status Bit 8 Security Level Word 91 Advanced power management level valueWord 89 Time required for Security erase unit completion Additional Requirements for CF Advanced Timing Modes Word 160 Power Requirement DescriptionValue Maximum PIO mode timing selected Value Current Multiword DMA timing mode selected Value Maximum Multiword DMA timing mode supportedValue Current PIO timing mode selected Value Maximum Pcmcia IO timing mode Supported Idle Immediate 95h or E1h Drive Cyl High Cyl Low Sec Num Sec Cnt FeatureIdle 97h or E3h Initialize Drive Parameters 91h Read Buffer E4h Read DMA C8h Read Multiple C4h Read Sectors 20h or 21h Read Verify Sectors 40h or 41h Recalibrate 1Xh Request Sense 03h Table Extended Error Codes Seek 7Xh Set Features EFh Table Feature Supported Set Multiple Mode C6h Set Sleep Mode- 99h or E6h Standby 96h or E2h TableTranslate Sector Information Standby Immediate 94h or E0hTranslate Sector 87h Write DMA CAh Wear Level F5hWrite Buffer E8h Write Multiple Command C5h Write Multiple without Erase CDh Write Sectors 30h or 31h Write Sectors without Erase 38h Write Verify 3Ch 80X CompactFlash Card Error Posting BBK UNC Idnf Abrt Amnf Drdy DWF DSC Corr ERR Address Data Description of Contents CIS function CIS Description Address Data 5 4 Description of Contents CIS function Cistplconfig V1.1 MS IR IO RO a Address Data 5 4 3 2 1 Description of Contents CIS function Irqn LS AS NR RO a T