Plug and Play Aware O/S
Set this option to Yes to inform AMIBIOS that the operating system can handle plug and Play (PnP) devices. The settings are No or Yes.
PCI Latency Timer (PCI Clocks)
This option specifies the latency timings (in PCI clocks) for PCI devices installed in the PCI expansion slots. The settings are 32, 64, 96, 128, 160, 192, 224, or 248.
PCI VGA Palette Snoop
When this option is set to Enabled, multiple VGA devices operating on different buses can handle data from the CPU on each set of palette registers on every video device. Bit 5 of the command register in the PCI device configuration space is the VGA Palette Snoop bit (0 is disabled). For example, if there are two VGA devices in the computer (one PCI and one ISA) and this field is set for:
Setting | Description | |
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Disabled | Data read and written by the CPU is only directed to the PCI VGA device's palette registers. | |
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Enabled | Data read and written by the CPU is directed to the both the PCI VGA device's palette registers and | |
the ISA VGA device palette registers, permitting the palette registers of both devices to be identical. | ||
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This option must be set to Enabled if any ISA adapter card installed in the system requires VGA palette snooping.
Allocate IRQ to PCI VGA
Set this option to Yes to allocate an IRQ to the VGA device on the PCI bus. The settings are Yes or No.
PCI IDE BusMaster
Set this option to Enabled to specify that the IDE controller on the PCI bus has bus mastering capability. The settings are Disabled or Enabled.
OffBoard PCI IDE Card
This option specifies whether or not an offboard PCI IDE controller adapter card is used in the computer, and where it is installed. If an offboard PCI IDE controller is used, the motherboard onboard IDE controller is automatically disabled. The settings are Auto and Slot1 through Slot6. If Auto is selected, AMIBIOS automatically determines the correct setting (including using the onboard controller if no offboard controller card is detected). This option forces IRQ 14 and 15 to a PCI slot on the PCI local bus. This is necessary to
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