NEC PD75P308 user manual DC Characteristics Ta = -10 to +70C, VDD = 5V ±5%, Reset

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μPD75P308

DC CHARACTERISTICS (Ta = -10 to +70°C, VDD = 5V ±5%)

Parameter

 

 

Symbol

 

 

Conditions

MIN.

TYP.

MAX.

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

High-Level Input Voltage

 

 

VIH1

 

Ports 2, 3

 

 

 

 

 

 

 

0.7 V

DD

 

 

DD

V

 

 

 

 

 

 

 

 

 

 

 

 

 

V

 

 

 

 

 

Ports 0, 1, 6, 7,

 

 

 

 

 

 

 

 

 

 

VIH2

 

RESET

0.8 VDD

 

VDD

V

 

 

 

VIH3

 

Ports 4, 5

 

 

Open-drain

0.7 VDD

 

 

10

V

 

 

 

VIH4

 

X1, X2, XT1

 

 

 

 

 

 

 

VDD-0.5

 

VDD

V

Low-Level Input Voltage

 

 

VIL1

 

Ports 2, 3, 4, 5

 

 

 

 

 

0

 

 

0.3 VDD

V

 

 

 

 

 

Ports 0, 1, 6, 7,

 

 

 

 

 

 

 

 

 

 

VIL2

 

RESET

0

 

 

0.2 VDD

V

 

 

 

VIL3

 

X1, X2, XT1

 

 

 

 

 

 

 

0

 

 

 

0.4

V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

High-Level Output Voltage

 

 

 

 

Ports 0, 2, 3,

IOH = -1mA

VDD-1.0

 

 

 

 

 

 

VOH1

6, 7

 

 

 

 

 

 

 

 

 

 

V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BIAS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VOH2

 

BP0-7

 

 

IOH = -100μA*1

VDD-2.0

 

 

 

V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Low-Level Output Voltage

 

 

 

 

Ports 0, 2, 3,

Ports 3, 4, 5

 

 

0.4

 

2.0

V

 

 

 

VOL1

6, 7

 

 

IOL = 15mA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IOL = 1.6mA

 

 

 

 

0.4

V

 

 

 

VOL2

 

SB0, 1

 

 

Pull-up R ≥ 1kΩ

 

 

 

0.2VDD

V

 

 

 

 

Open-drain

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VOL3

 

BP0-7

 

 

IOL = 100μA*1

 

 

 

 

1.0

V

High-Level Input Leakage Current

 

 

ILIH1

 

VIN = VDD

 

 

Other than below

 

 

 

 

3

μA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ILIH2

 

 

 

X1, X2, XT1

 

 

 

 

20

μA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ILIH3

 

VIN = 10V

 

 

Ports 4, 5

 

 

 

 

20

μA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Low-Level Input Leakage Current

 

 

ILIL1

 

VIN = 0V

 

 

Other than below

 

 

 

 

-3

μA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ILIL2

 

 

 

X1, X2, XT1

 

 

 

 

-20

μA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

High-Level Output Leakage Current

 

ILOH1

 

VOUT = VDD

 

 

Other than below

 

 

 

 

3

μA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ILOH2

 

VOUT = 10V

 

 

Ports 4.5

 

 

 

 

20

μA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Low-Level Output Leakage Current

 

 

ILOL

 

VOUT = 0V

 

 

 

 

 

 

 

 

 

 

 

-3

μA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Internal Pull-Up Resistor

 

 

RLI

 

Ports 0, 1, 2, 3, 6, 7

15

 

40

 

80

KΩ

 

 

 

 

(except P00) VIN = 0V

 

 

 

 

 

 

 

 

 

 

 

 

 

LCD Drive Voltage

 

 

VLCD

 

 

 

 

 

 

 

 

 

2.5

 

 

VDD

V

LCD Output Voltage Deviation

*2

 

 

I0 = ±5 μA

 

 

VLCD0 = VLCD

0

 

 

±

0.2V

V

 

 

 

ODC

 

 

 

2

 

 

(Common)

 

 

V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VLCD1 = VLCD x —

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3

 

 

 

 

 

 

 

*

2

 

 

 

 

 

 

 

 

 

 

 

LCD Output Voltage Deviation

 

 

 

 

 

1

 

 

 

 

 

 

 

VODS

 

I0 = ±1 μA

 

 

VLCD2 = VLCD x —

0

 

 

±0.2V

V

(Segment)

 

 

 

 

 

3

 

 

 

 

 

 

 

 

 

2.7 V ≤ VLCD ≤ VDD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Supply Current

*3

IDD1

 

4.19MHz crystal *4

*6

 

 

 

 

5

 

15

mA

 

 

 

 

 

oscillator

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IDD2

 

 

 

HALT mode

 

 

500

1500

μA

 

 

 

 

C1 = C2 = 22pF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IDD3

 

32 kHz

*5

 

 

 

 

 

 

 

 

350

1000

μA

 

 

 

 

crystal oscillator

 

 

HALT mode

 

 

35

100

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IDD4

 

XT1 = 0V

 

 

 

 

 

 

 

 

 

0.5

 

20

μA

 

 

 

 

STOP mode

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

*1: When using two of BP0-BP3 and two of BP4-BP7 for output at the same time.

2:"Voltage deviation" means the difference between the ideal segment or common output value (VLCDn: = 0, 1, 2) and output voltage.

3:Currents for the built-in pull-up resistor are not included.

4:Including when the subsystem clock is operated.

5:When operated with the subsystem clock by setting the system clock control register (SCC) to 1001 to stop the main system clock operation.

6:When operand in the high-speed mode with the processor clock control register (PCC) set to 0011.

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Contents Ordering Information FeaturesDescription Quality GradePIN Configuration ΜPD75P308Block Diagram Contents Port Pins PIN FunctionsNON Port Pins Schmitt trigger input with hysteresis characteristics PIN INPUT/OUTPUT CircuitsInput buffer of Cmos standard COM Type F-BIN/OUT SEG Connect capacitor between VDD and P00/INT4, Reset pin Type M-CDifferences Between μPD75P308 and μPD75308 EpromWriting and Verifying Prom Program Memory Program memory address 0 clear mode+12.5 Write mode Verify mode Program inhibit mode Or H Operation Modes for WRITING/VERIFYING Program MemoryProgram Memory Write Procedure VDD+1Program Memory Read Procedure Erasure μPD75P308K only Electrical Specifications Absolute Maximum Ratings Ta = 25CRecommended Oscillation Circuit Constants Main System Clock Oscillator Circuit CharacteristicsTa = -10 to +70C, VDD = 5 to ±5 Main System Clock Ceramic Oscillator Ta = -10 to +70CCapacitance Ta = 25C, VDD = 0 DC Characteristics Ta = -10 to +70C, VDD = 5V ±5% AC Characteristics Ta = -10 to + 70C, VDD = 5V ±5% Interrupt mode register IM0Operation Other Than Serial Transfer Serial Transfer Operation SBI Mode SCK internal clock output master SBI Mode SCK external clock output masterAC Timing Test Point excluding X1 and XT1 inputs Clock TimingTI0 Timing Serial Transfer Timing THREE-LINE Serial I/O Mode TWO-LINE Serial I/O ModeReset Input Timing Serial Transfer Timing BUS Release Signal TransferCommand Signal Transfer Interrupt Input TimingData Retention Timing releasing Stop mode by Reset Ta = -10 to +70CBTM3 BTM2 BTM1 BTM0 Other than X1 or Program Memory Write Timing Program Memory Read TimingMD0 MD1 Package Drawings PIN Plastic QFP 14×20PIN Ceramic Wqfn Millimeters InchesRecommended Soldering Conditions ΜPD75P308GF-3B9 80-pin plastic QFP 14 x 20 mmVPS Appendix A. Development Tools Prom writing toolsAppendix B. Related Documents Status Before Initialization ALL MOS Devices Processing of Unused Pins Cmos Devices onlyStatic Electricity ALL MOS Devices Fix the input level of Cmos devicesMemo
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