NEC PD75P308 user manual Serial Transfer Operation, Sck

Page 20

μPD75P308

SERIAL TRANSFER OPERATION

TWO-LINE AND THREE-LINE SERIAL I/O MODES (SCK: internal clock output)

 

 

 

 

 

Parameter

Symbol

Conditions

 

MIN.

TYP.

MAX.

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Cycle Time

 

 

Output

1600

 

 

ns

SCK

tKCY1

 

 

 

 

 

High-, Low-Level Widths

 

 

Output

tKCY1/2-50

 

 

ns

SCK

tKH1, tKL1

 

 

SI Set-Up Time (vs.

 

 

)

 

 

 

150

 

 

ns

SCK

tSIK1

 

 

 

SI Hold Time (vs.

 

)

 

 

 

400

 

 

ns

SCK

tKSI1

 

 

 

 

 

↓ → SO Output

 

RL = 1kΩ, CL = 100pF*

 

 

 

250

ns

SCK

tKSO1

 

 

 

Delay Time

 

 

 

 

 

 

 

*: RL and CL are load resistance and load capacitance of the SO output line.

TWO-LINE AND THREE-LINE SERIAL I/O MODES (SCK: external clock input)

 

 

 

 

 

Parameter

 

 

Symbol

Conditions

 

MIN.

TYP.

MAX.

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SCK Cycle Time

 

 

tKCY2

 

Input

800

 

 

ns

 

 

 

Input

400

 

 

ns

 

SCK

High-, Low-Level Widths

tKH2, tKL2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SI Set-Up Time (vs. SCK

)

tSIK2

 

 

100

 

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SI Hold Time (vs.

 

 

)

 

 

 

 

400

 

 

ns

SCK

 

tKSI2

 

 

 

 

 

 

 

 

 

↓ → SO Output

 

 

 

RL = 1kΩ, CL = 100pF*

 

 

 

300

ns

SCK

 

 

tKSO2

 

 

 

Delay Time

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

*: RL and CL are load resistance and load capacitance of the SO output line.

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Contents Features DescriptionOrdering Information Quality GradePIN Configuration ΜPD75P308Block Diagram Contents Port Pins PIN FunctionsNON Port Pins Input buffer of Cmos standard Schmitt trigger input with hysteresis characteristicsPIN INPUT/OUTPUT Circuits IN/OUT SEG COMType F-B Connect capacitor between VDD and P00/INT4, Reset pin Type M-CDifferences Between μPD75P308 and μPD75308 EpromProgram memory address 0 clear mode +12.5 Write mode Verify mode Program inhibit mode Or HWriting and Verifying Prom Program Memory Operation Modes for WRITING/VERIFYING Program MemoryProgram Memory Write Procedure VDD+1Program Memory Read Procedure Erasure μPD75P308K only Electrical Specifications Absolute Maximum Ratings Ta = 25CMain System Clock Oscillator Circuit Characteristics Ta = -10 to +70C, VDD = 5 to ±5Recommended Oscillation Circuit Constants Main System Clock Ceramic Oscillator Ta = -10 to +70CCapacitance Ta = 25C, VDD = 0 DC Characteristics Ta = -10 to +70C, VDD = 5V ±5% Operation Other Than Serial Transfer AC Characteristics Ta = -10 to + 70C, VDD = 5V ±5%Interrupt mode register IM0 Serial Transfer Operation SBI Mode SCK internal clock output master SBI Mode SCK external clock output masterTI0 Timing AC Timing Test Point excluding X1 and XT1 inputsClock Timing Serial Transfer Timing THREE-LINE Serial I/O Mode TWO-LINE Serial I/O ModeSerial Transfer Timing BUS Release Signal Transfer Command Signal TransferReset Input Timing Interrupt Input TimingBTM3 BTM2 BTM1 BTM0 Data Retention Timing releasing Stop mode by ResetTa = -10 to +70C Other than X1 or MD0 MD1 Program Memory Write TimingProgram Memory Read Timing Package Drawings PIN Plastic QFP 14×20PIN Ceramic Wqfn Millimeters InchesVPS Recommended Soldering ConditionsΜPD75P308GF-3B9 80-pin plastic QFP 14 x 20 mm Appendix A. Development Tools Prom writing toolsAppendix B. Related Documents Processing of Unused Pins Cmos Devices only Static Electricity ALL MOS DevicesStatus Before Initialization ALL MOS Devices Fix the input level of Cmos devicesMemo