NEC PD75P308 user manual Program Memory Read Procedure, MD2

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μPD75P308

3.3 PROGRAM MEMORY READ PROCEDURE

The contents of the program memory can be read in the following procedure.

(1)Ground the unused pins through pull-down resistors. The X1 pin must be low.

(2)Supply 5 V to the VDD and VPP pins.

(3)Wait for 10 microseconds.

(4)Set program memory address 0 clear mode.

(5)Supply 6 V to the VDD pin and 12.5 V to the VPP pin.

(6)Set program inhibit mode.

(7)Set verify mode. Data of each address is sequentially output each time a clock pulse is input to the X1 pin four times.

(8)Set program inhibit mode.

(9)Set program memory address 0 clear mode.

(10)Change the voltages of VDD and VPP pins to 5 V.

(11)Turn off the power supply.

Steps (2) to (9) are illustrated below.

VPP

VDD

VDD+1

VDD

X1
P40-P43	Data output	Data output
P50-P53	Data output	Data output
P50-P53

MD0

(P30)

MD1

(P31)

MD2

(P32)

MD3

(P33)

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Contents Description FeaturesOrdering Information Quality GradeΜPD75P308 PIN ConfigurationBlock Diagram Contents PIN Functions Port PinsNON Port Pins PIN INPUT/OUTPUT Circuits Schmitt trigger input with hysteresis characteristicsInput buffer of Cmos standard Type F-B COMIN/OUT SEG Type M-C Connect capacitor between VDD and P00/INT4, Reset pinEprom Differences Between μPD75P308 and μPD75308+12.5 Write mode Verify mode Program inhibit mode Or H Program memory address 0 clear modeWriting and Verifying Prom Program Memory Operation Modes for WRITING/VERIFYING Program MemoryVDD+1 Program Memory Write ProcedureProgram Memory Read Procedure Erasure μPD75P308K only Absolute Maximum Ratings Ta = 25C Electrical SpecificationsTa = -10 to +70C, VDD = 5 to ±5 Main System Clock Oscillator Circuit CharacteristicsRecommended Oscillation Circuit Constants Main System Clock Ceramic Oscillator Ta = -10 to +70CCapacitance Ta = 25C, VDD = 0 DC Characteristics Ta = -10 to +70C, VDD = 5V ±5% Interrupt mode register IM0 AC Characteristics Ta = -10 to + 70C, VDD = 5V ±5%Operation Other Than Serial Transfer Serial Transfer Operation SBI Mode SCK external clock output master SBI Mode SCK internal clock output masterClock Timing AC Timing Test Point excluding X1 and XT1 inputsTI0 Timing TWO-LINE Serial I/O Mode Serial Transfer Timing THREE-LINE Serial I/O ModeCommand Signal Transfer Serial Transfer Timing BUS Release Signal TransferReset Input Timing Interrupt Input TimingTa = -10 to +70C Data Retention Timing releasing Stop mode by ResetBTM3 BTM2 BTM1 BTM0 Other than X1 or Program Memory Read Timing Program Memory Write TimingMD0 MD1 PIN Plastic QFP 14×20 Package DrawingsMillimeters Inches PIN Ceramic WqfnΜPD75P308GF-3B9 80-pin plastic QFP 14 x 20 mm Recommended Soldering ConditionsVPS Prom writing tools Appendix A. Development ToolsAppendix B. Related Documents Static Electricity ALL MOS Devices Processing of Unused Pins Cmos Devices onlyStatus Before Initialization ALL MOS Devices Fix the input level of Cmos devicesMemo