NEC PD75P308 user manual PIN INPUT/OUTPUT Circuits, Input buffer of Cmos standard

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μPD75P308

1.3 PIN INPUT/OUTPUT CIRCUITS

The following shows a simplified input/output circuit diagram for each pin of the μPD75P308.

TYPE A (for TYPE E–B)		TYPE D (for TYPE E–B, F-A)
VDD
		data		P–ch
				P–ch
P–ch				OUT
IN				OUT
IN
N–ch		output		N–ch
		disable
Input buffer of CMOS standard		Push–pull output that can be set in a output
		high–impedance state (both P–ch and N–ch are off)
TYPE B		TYPE E–B		VDD
				VDD
				P.U.R.
			P.U.R.	P–ch
			enable	P–ch
			enable
IN		data
		data		IN/OUT
			Type D	IN/OUT
		output	Type D
		output
		disable
			Type A
Schmitt trigger input with hysteresis characteristics			P.U.R. : Pull–Up Resistor
TYPE B–C		TYPE E–E		VDD
				P.U.R.
VDD			P.U.R.
			P.U.R.	P–ch
P.U.R.			enable	P–ch
			enable

P–ch	P.U.R.	data		IN/OUT
P–ch	enable		Type D	IN/OUT
	enable	output	Type D
		output
		disable
IN
			Type A
P.U.R. : Pull–Up Resistor			Type B
P.U.R. : Pull–Up Resistor
Schmitt trigger input with hysteresis characteristics			P.U.R. : Pull–Up Resistor

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Contents Quality Grade FeaturesDescription Ordering InformationΜPD75P308 PIN ConfigurationBlock Diagram Contents PIN Functions Port PinsNON Port Pins PIN INPUT/OUTPUT Circuits Schmitt trigger input with hysteresis characteristicsInput buffer of Cmos standard Type F-B COMIN/OUT SEG Type M-C Connect capacitor between VDD and P00/INT4, Reset pinEprom Differences Between μPD75P308 and μPD75308Operation Modes for WRITING/VERIFYING Program Memory Program memory address 0 clear mode+12.5 Write mode Verify mode Program inhibit mode Or H Writing and Verifying Prom Program MemoryVDD+1 Program Memory Write ProcedureProgram Memory Read Procedure Erasure μPD75P308K only Absolute Maximum Ratings Ta = 25C Electrical SpecificationsMain System Clock Ceramic Oscillator Ta = -10 to +70C Main System Clock Oscillator Circuit CharacteristicsTa = -10 to +70C, VDD = 5 to ±5 Recommended Oscillation Circuit ConstantsCapacitance Ta = 25C, VDD = 0 DC Characteristics Ta = -10 to +70C, VDD = 5V ±5% Interrupt mode register IM0 AC Characteristics Ta = -10 to + 70C, VDD = 5V ±5%Operation Other Than Serial Transfer Serial Transfer Operation SBI Mode SCK external clock output master SBI Mode SCK internal clock output masterClock Timing AC Timing Test Point excluding X1 and XT1 inputsTI0 Timing TWO-LINE Serial I/O Mode Serial Transfer Timing THREE-LINE Serial I/O ModeInterrupt Input Timing Serial Transfer Timing BUS Release Signal TransferCommand Signal Transfer Reset Input TimingTa = -10 to +70C Data Retention Timing releasing Stop mode by ResetBTM3 BTM2 BTM1 BTM0 Other than X1 or Program Memory Read Timing Program Memory Write TimingMD0 MD1 PIN Plastic QFP 14×20 Package DrawingsMillimeters Inches PIN Ceramic WqfnΜPD75P308GF-3B9 80-pin plastic QFP 14 x 20 mm Recommended Soldering ConditionsVPS Prom writing tools Appendix A. Development ToolsAppendix B. Related Documents Fix the input level of Cmos devices Processing of Unused Pins Cmos Devices onlyStatic Electricity ALL MOS Devices Status Before Initialization ALL MOS DevicesMemo

μPD75P308

1.3 PIN INPUT/OUTPUT CIRCUITS

Input buffer of CMOS standard

TYPE B

TYPE B–C

Schmitt trigger input with hysteresis characteristics