μPD75P308
AC CHARACTERISTICS (Ta = -10 to + 70°C, VDD = 5V ±5%)
Operation Other Than Serial Transfer
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| MIN. | TYP. |
| MAX. | Unit | |||||||
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| CPU Clock Cycle Time*1 |
| w/main system clock |
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| 0.95 |
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| 64 | μs | |||||||||
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| (Minimum Instruction |
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| Execution Time | tCY |
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| w/subsystem clock |
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| 114 | 122 | 125 | μs | ||||||||||||
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| = 1 Machine Cycle) |
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| TI0 Input Frequency | fTI |
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| 0 |
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| 1 | MHz | ||||
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| TI0 Input | tTIH, tTIL |
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| 0.48 |
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| Interrupt Input | tINTH, | INT0 |
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| *2 |
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| μs | ||
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| tINTL |
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| Widths |
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| 10 |
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| tRSL |
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| 10 |
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| RESET |
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| t cy vs VDD |
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| 70 |
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| (with main system clock) | ||||||
* 1: The CPU clock (Φ) cycle time is determined |
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| by the oscillation frequency of the connected |
| 64 |
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| 60 |
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| oscillator, system clock control register |
| 6 |
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| (SCC), and processor clock control register |
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| (PCC). |
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| 5 |
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| The figure on the right is cycle time tCY vs. |
| 4 |
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| supply voltage VDD characteristics at the | s] |
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| main system clock. |
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| μ[ | 3 |
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| cy |
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| 2: 2tCY or 128/fXX depending on the setting of | t |
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| time |
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| the interrupt mode register (IM0). | 2 |
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| Cycle |
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| 1 |
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| 0.5 |
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| 0 |
| 1 | 2 | 3 | 4 | 5 |
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| Supply voltage V | [V] |
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| DD |
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19