NEC PD75P308 SBI Mode SCK internal clock output master, SBI Mode SCK external clock output master

Page 21

μPD75P308

SBI MODE (SCK: internal clock output (master))

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

1600

ns

SCK

Cycle Time

tKCY3

tKL3

tKCY/2

SCK

High-, Low-Level

ns

Widths

tKH3

-50

SB0, 1 Set-Up Time (vs.

− )

tSIK3

SCK

150

ns

SB0, 1 Hold Time (vs.

− )

tKSI3

SCK

tKCY/2

ns

↓ → SB0, 1 Output

SCK

tKSO3

RL = 1kΩ, CL = 100pF*

0

250

ns

Delay Time

− →

↓

tKSB

SCK

tKCY

ns

SB0, 1

SB0, 1

↓ →

↓

tSBK

tKCY

ns

SCK

SB0, 1 Low-Level Width

tSBL

tKCY

ns

SB0, 1 High-Level Width

tSBH

tKCY

ns

*: RL and CL are load resistance and load capacitance of the SO output line.

SBI MODE (SCK: external clock output (master))

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

1600

ns

SCK

Cycle Time

tKCY4

tKL4

SCK High-, Low-Level

400

ns

Widths

tKH4

SB0, 1 Set-Up Time (vs.

− )

tSIK4

SCK

100

ns

SB0, 1 Hold Time (vs.

− )

tKSI4

SCK

tKCY/2

ns

↓ → SB0, 1 Output

SCK

tKSO4

RL = 1kΩ, CL = 100pF*

0

300

ns

Delay Time

− →

↓

tKSB

SCK

tKCY

ns

SB0, 1

SB0, 1 ↓ →

↓

tSBK

tKCY

ns

SCK

SB0, 1 Low-Level Width

tSBL

tKCY

ns

SB0, 1 High-Level Width

tSBH

tKCY

ns

*: RL and CL are load resistance and load capacitance of the SO output line.

★

★

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Contents Description FeaturesOrdering Information Quality GradeΜPD75P308 PIN ConfigurationBlock Diagram Contents PIN Functions Port PinsNON Port Pins Schmitt trigger input with hysteresis characteristics PIN INPUT/OUTPUT CircuitsInput buffer of Cmos standard COM Type F-BIN/OUT SEG Type M-C Connect capacitor between VDD and P00/INT4, Reset pinEprom Differences Between μPD75P308 and μPD75308+12.5 Write mode Verify mode Program inhibit mode Or H Program memory address 0 clear modeWriting and Verifying Prom Program Memory Operation Modes for WRITING/VERIFYING Program MemoryVDD+1 Program Memory Write ProcedureProgram Memory Read Procedure Erasure μPD75P308K only Absolute Maximum Ratings Ta = 25C Electrical SpecificationsTa = -10 to +70C, VDD = 5 to ±5 Main System Clock Oscillator Circuit CharacteristicsRecommended Oscillation Circuit Constants Main System Clock Ceramic Oscillator Ta = -10 to +70CCapacitance Ta = 25C, VDD = 0 DC Characteristics Ta = -10 to +70C, VDD = 5V ±5% AC Characteristics Ta = -10 to + 70C, VDD = 5V ±5% Interrupt mode register IM0Operation Other Than Serial Transfer Serial Transfer Operation SBI Mode SCK external clock output master SBI Mode SCK internal clock output masterAC Timing Test Point excluding X1 and XT1 inputs Clock TimingTI0 Timing TWO-LINE Serial I/O Mode Serial Transfer Timing THREE-LINE Serial I/O ModeCommand Signal Transfer Serial Transfer Timing BUS Release Signal TransferReset Input Timing Interrupt Input TimingData Retention Timing releasing Stop mode by Reset Ta = -10 to +70CBTM3 BTM2 BTM1 BTM0 Other than X1 or Program Memory Write Timing Program Memory Read TimingMD0 MD1 PIN Plastic QFP 14×20 Package DrawingsMillimeters Inches PIN Ceramic WqfnRecommended Soldering Conditions ΜPD75P308GF-3B9 80-pin plastic QFP 14 x 20 mmVPS Prom writing tools Appendix A. Development ToolsAppendix B. Related Documents Static Electricity ALL MOS Devices Processing of Unused Pins Cmos Devices onlyStatus Before Initialization ALL MOS Devices Fix the input level of Cmos devicesMemo