Texas Instruments TMS320C642x DSP Protocol Descriptions, DDR2 Sdram Commands, Command Function

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Peripheral Architecture

2.4Protocol Description(s)

The DDR2 memory controller supports the DDR2 SDRAM commands listed in Table 3. Table 4 shows the signal truth table for the DDR2 SDRAM commands.

	Table 3. DDR2 SDRAM Commands
Command	Function
ACTV	Activates the selected bank and row.
DCAB	Precharge all command. Deactivates (precharges) all banks.
DEAC	Precharge single command. Deactivates (precharges) a single bank.
DESEL	Device Deselect.
EMRS	Extended Mode Register set. Allows altering the contents of the mode register.
MRS	Mode register set. Allows altering the contents of the mode register.
NOP	No operation.
Power Down	Power down mode.
READ	Inputs the starting column address and begins the read operation.
READ with	Inputs the starting column address and begins the read operation. The read operation is followed by a
autoprecharge	precharge.
REFR	Autorefresh cycle.
SLFREFR	Self-refresh mode.
WRT	Inputs the starting column address and begins the write operation.
WRT with	Inputs the starting column address and begins the write operation. The write operation is followed by a
autoprecharge	precharge.

Table 4. Truth Table for DDR2 SDRAM Commands

DDR2
SDRAM:	CKE		CS	RAS	CAS	WE	BA[2:0]	A[12:11, 9:0]	A10
DDR2
memory
controller:		DDR_CKE	DDR_CS	DDR_RAS	DDR_CAS	DDR_WE	DDR_BA[2:0]	DDR_A[12:11, 9:0]	DDR_A[10]
	Previous
	Cycles	Current Cycle
ACTV	H	H	L	L	H	H	Bank	Row Address
DCAB	H	H	L	L	H	L	X	X	L
DEAC	H	H	L	L	H	L	Bank	X	L
MRS	H	H	L	L	L	L	BA	OP Code
EMRS	H	H	L	L	L	L	BA	OP Code
READ	H	H	L	H	L	H	BA	Column Address	L
READ with	H	H	L	H	L	H	BA	Column Address	H
precharge
WRT	H	H	L	H	L	L	BA	Column Address	L
WRT with	H	H	L	H	L	L	BA	Column Address	L
precharge
REFR	H	H	L	L	L	H	X	X	X
SLFREFR	H	L	L	L	L	H	X	X	X
entry
SLFREFR	L	H	H	X	X	X	X	X	X
exit			L	H	H	H	X	X	X
			L	H	H	H	X	X	X
NOP	H	X	L	H	H	H	X	X	X
DESEL	H	X	H	X	X	X	X	X	X
Power Down	H	L	H	X	X	X	X	X	X
entry			L	H	H	H	X	X	X
			L	H	H	H	X	X	X
Power Down	L	H	H	X	X	X	X	X	X
exit			L	H	H	H	X	X	X
			L	H	H	H	X	X	X

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DDR2 Memory Controller

SPRUEM4A–November 2007

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Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Features Purpose of the PeripheralFunctional Block Diagram Supported Use Case StatementIndustry Standards Compliance Statement Clock Control Clock SourceClock Configuration PLLC2 ConfigurationMemory Map 3 DDR2 Memory Controller Internal Clock DomainsSignal Descriptions DDR2 Memory Controller Signal DescriptionsClock enable Active high Pin Type DescriptionDDR2 Sdram Commands Truth Table for DDR2 Sdram CommandsCommand Function Protocol DescriptionsRefresh Mode Refresh CommandDcab Command Deactivation Dcab and DeacDeac Command Actv Command Activation ActvRead Command DDR2 Read CommandWrite WRT Command DDR2 WRT CommandMode Register Set MRS and Emrs DDR2 MRS and Emrs CommandMemory Width and Byte Alignment Addressable Memory RangesEndianness Support Bit External MemoryBank Configuration Register Fields for Address Mapping Address MappingBit Field Bit Value Bit Description Logical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram Logical Address-to-DDR2 Sdram Address Map for 16-bit SdramLogical Address-to-DDR2 Sdram Address Map DDR2 Sdram Column, Row, and Bank Access DDR2 Memory Controller Interface DDR2 Memory Controller Fifo DescriptionCommand Ordering and Scheduling, Advanced Concept Command Starvation Possible Race ConditionSelf-Refresh Mode Refresh SchedulingRefresh Urgency Levels Urgency Level DescriptionReset Considerations Reset SourcesReset Signal Reset Source VTP IO Buffer Calibration Auto-Initialization SequenceDDR2 Sdram Configuration by MRS Command DDR2 Sdram Configuration by EMRS1 CommandInitializing Configuration Registers DDR2 Memory ControllerPeripheral Architecture Power Management Interrupt SupportDMA Event Support Emulation Considerations Connecting the DDR2 Memory Controller to DDR2 Memory Supported Use CasesConnecting DDR2 Memory Controller for 32-Bit Connection Configuring Sdram Bank Configuration Register Sdbcr Sdram Bank Configuration Register Sdbcr ConfigurationConfiguring Sdram Refresh Control Register Sdrcr DDR2 Memory Refresh SpecificationConfiguring Sdram Timing Registers Sdtimr and SDTIMR2 Sdram Timing Register Sdtimr ConfigurationSdram Timing Register 2 SDTIMR2 Configuration DDR2 Data Register Field Manual Data Manual FormulaConfiguring DDR PHY Control Register Ddrphycr DDR PHY Control Register Ddrphycr ConfigurationRegister Field Name Description Mode D63-32 D31-0Acronym Register Description DDR VTP RegisterSdram Status Register Sdrstat Sdram Status Register Sdrstat Field DescriptionsBit Field Sdram Bank Configuration Register Sdbcr Sdram Bank Configuration Register Sdbcr Field DescriptionsBit Field Value Description Reserved Reserved. Always write a 0 to this bit Sdram Refresh Control Register Sdrcr Sdram Refresh Control Register Sdrcr Field DescriptionsSdram Timing Register Sdtimr Sdram Timing Register Sdtimr Field DescriptionsSdram Timing Register 2 SDTIMR2 Sdram Timing Register 2 SDTIMR2 Field DescriptionsPeripheral Bus Burst Priority Register Pbbpr Peripheral Bus Burst Priority Register PbbprInterrupt Raw Register IRR Interrupt Raw Register IRR Field DescriptionsInterrupt Masked Register IMR Interrupt Masked Register IMR Field DescriptionsInterrupt Mask Set Register Imsr Interrupt Mask Set Register Imsr Field DescriptionsInterrupt Mask Clear Register Imcr Interrupt Mask Clear Register Imcr Field DescriptionsDDR PHY Control Register Ddrphycr DDR PHY Control Register Ddrphycr Field DescriptionsVTP IO Control Register Vtpiocr VTP IO Control Register Vtpiocr Field DescriptionsDDR VTP Enable Register Ddrvtper DDR VTP Enable Register Ddrvtper Field DescriptionsDDR VTP Register Ddrvtpr DDR VTP Register Ddrvtpr Field DescriptionsTable A-1. Document Revision History Additions/Modifications/DeletionsImportant Notice