Texas Instruments TMS320C642x DSP manual Configuring Sdram Timing Registers Sdtimr and SDTIMR2

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Supported Use Cases

3.2.3Configuring SDRAM Timing Registers (SDTIMR and SDTIMR2)

The SDRAM timing register (SDTIMR) and SDRAM timing register 2 (SDTIMR2) configure the DDR2 memory controller to meet the data sheet timing parameters of the attached DDR2 device. Each field in SDTIMR and SDTIMR2 corresponds to a timing parameter in the DDR2 data sheet specification. Table 19 and Table 20 display the register field name and corresponding DDR2 data sheet parameter name along with the data sheet value. These tables also provide a formula to calculate the register field value and displays the resulting calculation. Each of the equations include a minus 1 because the register fields are defined in terms of DDR2 clock cycles minus 1. See Section 4.4 and Section 4.5 for more information.

Table 19. SDRAM Timing Register (SDTIMR) Configuration

	DDR2 Data
Register Field	Manual		Data Manual	Formula	Register
Name	Parameter Name	Description	Value (nS)	(Register field must be ≥)	Value
T_RFC	tRFC	Refresh cycle time	127.5	(tRFC × fDDR2_CLK) - 1	16
T_RP	tRP	Precharge command to	20	(tRP × fDDR2_CLK) - 1	2
		refresh or activate
		command
T_RCD	tRCD	Activate command to	20	(tRCD × fDDR2_CLK) - 1	2
		read/write command
T_WR	tWR	Write recovery time	15	(tWR × fDDR2_CLK) - 1	1
T_RAS	tRAS	Active to precharge	45	(tRAC × fDDR2_CLK) - 1	5
		command
T_RC	tRC	Activate to Activate	65	(tRC × fDDR2_CLK) - 1	8
		command in the same
		bank
T_RRD	tRRD	Activate to Activate	10	((4 × tRRD) + (2 × tCK))/(4 × tCK) - 1	1
		command in a different
		bank
T_WTR	tWTR	Write to read command	10	(tWTR × fDDR2_CLK) - 1	1
		delay

Note: The equation given above for the T_RRD field applies only for 8 bank DDR2 memories. When interfacing to DDR2 memories with less than 8 banks, the T_RRD field should be calculated using the following equation (tRRD × fDDR2_CLK) - 1.

Table 20. SDRAM Timing Register 2 (SDTIMR2) Configuration

	DDR2 Data
Register Field	Manual		Data Manual	Formula (Register	Register
Name	Parameter Name	Description	Value	field must be ≥)	Value
T_XSNR	tXSNR	Exit self refresh to a non-read	137.5 nS	(tXSNR × fDDR2_CLK) - 1	18
		command
T_XSRD	tXSRD	Exit self refresh to a read	200 (tCK cycles)	tXSRD - 1	199
		command
T_RTP	tRTP	Read to precharge command delay	7.5 nS	(tRTP × fDDR2_CLK) - 1	1
T_CKE	tCKE	CKE minimum pulse width	3 (tCK cycles)	tCKE - 1	2

SPRUEM4A–November 2007	DDR2 Memory Controller	39
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Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Purpose of the Peripheral FeaturesFunctional Block Diagram Supported Use Case StatementIndustry Standards Compliance Statement Clock Source Clock Control3 DDR2 Memory Controller Internal Clock Domains Clock ConfigurationPLLC2 Configuration Memory MapPin Type Description Signal DescriptionsDDR2 Memory Controller Signal Descriptions Clock enable Active highProtocol Descriptions DDR2 Sdram CommandsTruth Table for DDR2 Sdram Commands Command FunctionRefresh Command Refresh ModeDeactivation Dcab and Deac Dcab CommandDeac Command Activation Actv Actv CommandDDR2 Read Command Read CommandDDR2 WRT Command Write WRT CommandDDR2 MRS and Emrs Command Mode Register Set MRS and EmrsAddressable Memory Ranges Memory Width and Byte AlignmentBit External Memory Endianness SupportBank Configuration Register Fields for Address Mapping Address MappingBit Field Bit Value Bit Description Logical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map for 32-Bit SdramLogical Address-to-DDR2 Sdram Address Map DDR2 Sdram Column, Row, and Bank Access DDR2 Memory Controller Fifo Description DDR2 Memory Controller InterfaceCommand Ordering and Scheduling, Advanced Concept Possible Race Condition Command StarvationUrgency Level Description Self-Refresh ModeRefresh Scheduling Refresh Urgency LevelsReset Considerations Reset SourcesReset Signal Reset Source Auto-Initialization Sequence VTP IO Buffer CalibrationDDR2 Memory Controller DDR2 Sdram Configuration by MRS CommandDDR2 Sdram Configuration by EMRS1 Command Initializing Configuration RegistersPeripheral Architecture Power Management Interrupt SupportDMA Event Support Emulation Considerations Supported Use Cases Connecting the DDR2 Memory Controller to DDR2 MemoryConnecting DDR2 Memory Controller for 32-Bit Connection DDR2 Memory Refresh Specification Configuring Sdram Bank Configuration Register SdbcrSdram Bank Configuration Register Sdbcr Configuration Configuring Sdram Refresh Control Register SdrcrDDR2 Data Register Field Manual Data Manual Formula Configuring Sdram Timing Registers Sdtimr and SDTIMR2Sdram Timing Register Sdtimr Configuration Sdram Timing Register 2 SDTIMR2 ConfigurationConfiguring DDR PHY Control Register Ddrphycr DDR PHY Control Register Ddrphycr ConfigurationRegister Field Name Description DDR VTP Register Mode D63-32D31-0 Acronym Register DescriptionSdram Status Register Sdrstat Sdram Status Register Sdrstat Field DescriptionsBit Field Sdram Bank Configuration Register Sdbcr Sdram Bank Configuration Register Sdbcr Field DescriptionsBit Field Value Description Reserved Reserved. Always write a 0 to this bit Sdram Refresh Control Register Sdrcr Field Descriptions Sdram Refresh Control Register SdrcrSdram Timing Register Sdtimr Field Descriptions Sdram Timing Register SdtimrSdram Timing Register 2 SDTIMR2 Field Descriptions Sdram Timing Register 2 SDTIMR2Peripheral Bus Burst Priority Register Pbbpr Peripheral Bus Burst Priority Register PbbprInterrupt Raw Register IRR Field Descriptions Interrupt Raw Register IRRInterrupt Masked Register IMR Field Descriptions Interrupt Masked Register IMRInterrupt Mask Set Register Imsr Field Descriptions Interrupt Mask Set Register ImsrInterrupt Mask Clear Register Imcr Field Descriptions Interrupt Mask Clear Register ImcrDDR PHY Control Register Ddrphycr Field Descriptions DDR PHY Control Register DdrphycrVTP IO Control Register Vtpiocr Field Descriptions VTP IO Control Register VtpiocrDDR VTP Register Ddrvtpr Field Descriptions DDR VTP Enable Register DdrvtperDDR VTP Enable Register Ddrvtper Field Descriptions DDR VTP Register DdrvtprAdditions/Modifications/Deletions Table A-1. Document Revision HistoryImportant Notice