Texas Instruments TMS320C642x DSP manual List of Tables

Page 5

	List of Tables
1	PLLC2 Configuration	10
2	DDR2 Memory Controller Signal Descriptions	11
3	DDR2 SDRAM Commands	12
4	Truth Table for DDR2 SDRAM Commands	12
5	Addressable Memory Ranges	20
6	16-Bit External Memory	21
7	32-Bit External Memory	21
8	Bank Configuration Register Fields for Address Mapping	22
9	Logical Address-to-DDR2 SDRAM Address Map for 32-Bit SDRAM	23
10	Logical Address-to-DDR2 SDRAM Address Map for 16-bit SDRAM	23
11	DDR2 Memory Controller FIFO Description	26
12	Refresh Urgency Levels	29
13	Reset Sources	30
14	DDR2 SDRAM Configuration by MRS Command	32
15	DDR2 SDRAM Configuration by EMRS(1) Command	32
16	SDRAM Bank Configuration Register (SDBCR) Configuration	38
17	DDR2 Memory Refresh Specification	38
18	SDRAM Refresh Control Register (SDRCR) Configuration	38
19	SDRAM Timing Register (SDTIMR) Configuration	39
20	SDRAM Timing Register 2 (SDTIMR2) Configuration	39
21	DDR PHY Control Register (DDRPHYCR) Configuration	40
22	DDR2 Memory Controller Registers Relative to Base Address 2000 0000h	41
23	DDR2 Memory Controller Registers Relative to Base Address 01C4 2000h	41
24	DDR2 Memory Controller Registers Relative to Base Address 01C4 0000h	41
25	SDRAM Status Register (SDRSTAT) Field Descriptions	42
26	SDRAM Bank Configuration Register (SDBCR) Field Descriptions	43
27	SDRAM Refresh Control Register (SDRCR) Field Descriptions	45
28	SDRAM Timing Register (SDTIMR) Field Descriptions	46
29	SDRAM Timing Register 2 (SDTIMR2) Field Descriptions	47
30	Peripheral Bus Burst Priority Register (PBBPR) Field Descriptions	48
31	Interrupt Raw Register (IRR) Field Descriptions	49
32	Interrupt Masked Register (IMR) Field Descriptions	50
33	Interrupt Mask Set Register (IMSR) Field Descriptions	51
34	Interrupt Mask Clear Register (IMCR) Field Descriptions	52
35	DDR PHY Control Register (DDRPHYCR) Field Descriptions	53
36	VTP IO Control Register (VTPIOCR) Field Descriptions	54
37	DDR VTP Register (DDRVTPR) Field Descriptions	55
38	DDR VTP Enable Register (DDRVTPER) Field Descriptions	55
A-1	Document Revision History	56

SPRUEM4A–November 2007

List of Tables

5

Submit Documentation Feedback

Image 5

Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Purpose of the Peripheral FeaturesIndustry Standards Compliance Statement Functional Block DiagramSupported Use Case Statement Clock Source Clock ControlPLLC2 Configuration Clock ConfigurationMemory Map 3 DDR2 Memory Controller Internal Clock DomainsDDR2 Memory Controller Signal Descriptions Signal DescriptionsClock enable Active high Pin Type DescriptionTruth Table for DDR2 Sdram Commands DDR2 Sdram CommandsCommand Function Protocol DescriptionsRefresh Command Refresh ModeDeactivation Dcab and Deac Dcab CommandDeac Command Activation Actv Actv CommandDDR2 Read Command Read CommandDDR2 WRT Command Write WRT CommandDDR2 MRS and Emrs Command Mode Register Set MRS and EmrsAddressable Memory Ranges Memory Width and Byte AlignmentBit External Memory Endianness SupportBit Field Bit Value Bit Description Bank Configuration Register Fields for Address MappingAddress Mapping Logical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map for 32-Bit SdramLogical Address-to-DDR2 Sdram Address Map DDR2 Sdram Column, Row, and Bank Access DDR2 Memory Controller Fifo Description DDR2 Memory Controller InterfaceCommand Ordering and Scheduling, Advanced Concept Possible Race Condition Command StarvationRefresh Scheduling Self-Refresh ModeRefresh Urgency Levels Urgency Level DescriptionReset Signal Reset Source Reset ConsiderationsReset Sources Auto-Initialization Sequence VTP IO Buffer CalibrationDDR2 Sdram Configuration by EMRS1 Command DDR2 Sdram Configuration by MRS CommandInitializing Configuration Registers DDR2 Memory ControllerPeripheral Architecture DMA Event Support Power ManagementInterrupt Support Emulation Considerations Supported Use Cases Connecting the DDR2 Memory Controller to DDR2 MemoryConnecting DDR2 Memory Controller for 32-Bit Connection Sdram Bank Configuration Register Sdbcr Configuration Configuring Sdram Bank Configuration Register SdbcrConfiguring Sdram Refresh Control Register Sdrcr DDR2 Memory Refresh SpecificationSdram Timing Register Sdtimr Configuration Configuring Sdram Timing Registers Sdtimr and SDTIMR2Sdram Timing Register 2 SDTIMR2 Configuration DDR2 Data Register Field Manual Data Manual FormulaRegister Field Name Description Configuring DDR PHY Control Register DdrphycrDDR PHY Control Register Ddrphycr Configuration D31-0 Mode D63-32Acronym Register Description DDR VTP RegisterBit Field Sdram Status Register SdrstatSdram Status Register Sdrstat Field Descriptions Bit Field Value Description Sdram Bank Configuration Register SdbcrSdram Bank Configuration Register Sdbcr Field Descriptions Reserved Reserved. Always write a 0 to this bit Sdram Refresh Control Register Sdrcr Field Descriptions Sdram Refresh Control Register SdrcrSdram Timing Register Sdtimr Field Descriptions Sdram Timing Register SdtimrSdram Timing Register 2 SDTIMR2 Field Descriptions Sdram Timing Register 2 SDTIMR2Peripheral Bus Burst Priority Register Pbbpr Peripheral Bus Burst Priority Register PbbprInterrupt Raw Register IRR Field Descriptions Interrupt Raw Register IRRInterrupt Masked Register IMR Field Descriptions Interrupt Masked Register IMRInterrupt Mask Set Register Imsr Field Descriptions Interrupt Mask Set Register ImsrInterrupt Mask Clear Register Imcr Field Descriptions Interrupt Mask Clear Register ImcrDDR PHY Control Register Ddrphycr Field Descriptions DDR PHY Control Register DdrphycrVTP IO Control Register Vtpiocr Field Descriptions VTP IO Control Register VtpiocrDDR VTP Enable Register Ddrvtper Field Descriptions DDR VTP Enable Register DdrvtperDDR VTP Register Ddrvtpr DDR VTP Register Ddrvtpr Field DescriptionsAdditions/Modifications/Deletions Table A-1. Document Revision HistoryImportant Notice