Texas Instruments TMS320C642x DSP manual Sdram Timing Register 2 SDTIMR2

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DDR2 Memory Controller Registers

4.5SDRAM Timing Register 2 (SDTIMR2)

Like the SDRAM timing register (SDTIMR), the SDRAM timing register 2 (SDTIMR2) also configures the DDR2 memory controller to meet the AC timing specification of the DDR2 memory. The SDTIMR2 register is programmable only when the TIMUNLOCK bit is set to 1 in the SDBCR. See the DDR2 data sheet for information on the appropriate values to program each field. SDTIMR2 is shown in Figure 23 and described in Table 29.

Figure 23. SDRAM Timing Register 2 (SDTIMR2)

31	25	24	23	22		16
Reserved		Reserved				T_XSNR
R-0			R/W-x			R/W-1Dh
15		8	7	5	4	0
T_XSRD				T_RTP		T_CKE
R/W-F1h				R/W-2h		R/W-5h

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset; -x = value is indeterminate after reset

Table 29. SDRAM Timing Register 2 (SDTIMR2) Field Descriptions

Bit	Field	Value	Description
31-25	Reserved	0	Reserved
24-23	Reserved	x	Reserved. Reset value is indeterminate.
22-16	T_XSNR	0-7Fh	Specifies the minimum number of DDR_CLK cycles from a self-refresh exit to any other command
			except a read command, minus 1. Corresponds to the txsnr AC timing parameter in the DDR2 data
			sheet. Calculate by:
			T_XSNR = (txsnr/DDR_CLK period) - 1
15-8	T_XSRD	0-FFh	Specifies the minimum number of DDR_CLK cycles from a self-refresh exit to a read command,
			minus 1. Corresponds to the txsrd AC timing parameter in the DDR2 data sheet. Calculate by:
			T_XSRD = txsrd - 1
7-5	T_RTP	0-7h	Specifies the minimum number of DDR_CLK cycles from a last read command to a precharge
			command, minus 1. Corresponds to the trtp AC timing parameter in the DDR2 data sheet. Calculate by:
			T_RTP = (trtp/DDR_CLK period) - 1
4-0	T_CKE	0-1Fh	Specifies the minimum number of DDR_CLK cycles between transitions on the DDR_CKE pin, minus 1.
			Corresponds to the tcke AC timing parameter in the DDR2 data sheet. Calculate by:

T_CKE = tcke - 1

SPRUEM4A–November 2007	DDR2 Memory Controller	47
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Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Purpose of the Peripheral FeaturesIndustry Standards Compliance Statement Functional Block DiagramSupported Use Case Statement Clock Source Clock Control3 DDR2 Memory Controller Internal Clock Domains Clock ConfigurationPLLC2 Configuration Memory MapPin Type Description Signal DescriptionsDDR2 Memory Controller Signal Descriptions Clock enable Active highProtocol Descriptions DDR2 Sdram CommandsTruth Table for DDR2 Sdram Commands Command FunctionRefresh Command Refresh ModeDeactivation Dcab and Deac Dcab CommandDeac Command Activation Actv Actv CommandDDR2 Read Command Read CommandDDR2 WRT Command Write WRT CommandDDR2 MRS and Emrs Command Mode Register Set MRS and EmrsAddressable Memory Ranges Memory Width and Byte AlignmentBit External Memory Endianness SupportBit Field Bit Value Bit Description Bank Configuration Register Fields for Address MappingAddress Mapping Logical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map for 32-Bit SdramLogical Address-to-DDR2 Sdram Address Map DDR2 Sdram Column, Row, and Bank Access DDR2 Memory Controller Fifo Description DDR2 Memory Controller InterfaceCommand Ordering and Scheduling, Advanced Concept Possible Race Condition Command StarvationUrgency Level Description Self-Refresh ModeRefresh Scheduling Refresh Urgency LevelsReset Signal Reset Source Reset ConsiderationsReset Sources Auto-Initialization Sequence VTP IO Buffer CalibrationDDR2 Memory Controller DDR2 Sdram Configuration by MRS CommandDDR2 Sdram Configuration by EMRS1 Command Initializing Configuration RegistersPeripheral Architecture DMA Event Support Power ManagementInterrupt Support Emulation Considerations Supported Use Cases Connecting the DDR2 Memory Controller to DDR2 MemoryConnecting DDR2 Memory Controller for 32-Bit Connection DDR2 Memory Refresh Specification Configuring Sdram Bank Configuration Register SdbcrSdram Bank Configuration Register Sdbcr Configuration Configuring Sdram Refresh Control Register SdrcrDDR2 Data Register Field Manual Data Manual Formula Configuring Sdram Timing Registers Sdtimr and SDTIMR2Sdram Timing Register Sdtimr Configuration Sdram Timing Register 2 SDTIMR2 ConfigurationRegister Field Name Description Configuring DDR PHY Control Register DdrphycrDDR PHY Control Register Ddrphycr Configuration DDR VTP Register Mode D63-32D31-0 Acronym Register DescriptionBit Field Sdram Status Register SdrstatSdram Status Register Sdrstat Field Descriptions Bit Field Value Description Sdram Bank Configuration Register SdbcrSdram Bank Configuration Register Sdbcr Field Descriptions Reserved Reserved. Always write a 0 to this bit Sdram Refresh Control Register Sdrcr Field Descriptions Sdram Refresh Control Register SdrcrSdram Timing Register Sdtimr Field Descriptions Sdram Timing Register SdtimrSdram Timing Register 2 SDTIMR2 Field Descriptions Sdram Timing Register 2 SDTIMR2Peripheral Bus Burst Priority Register Pbbpr Peripheral Bus Burst Priority Register PbbprInterrupt Raw Register IRR Field Descriptions Interrupt Raw Register IRRInterrupt Masked Register IMR Field Descriptions Interrupt Masked Register IMRInterrupt Mask Set Register Imsr Field Descriptions Interrupt Mask Set Register ImsrInterrupt Mask Clear Register Imcr Field Descriptions Interrupt Mask Clear Register ImcrDDR PHY Control Register Ddrphycr Field Descriptions DDR PHY Control Register DdrphycrVTP IO Control Register Vtpiocr Field Descriptions VTP IO Control Register VtpiocrDDR VTP Register Ddrvtpr Field Descriptions DDR VTP Enable Register DdrvtperDDR VTP Enable Register Ddrvtper Field Descriptions DDR VTP Register DdrvtprAdditions/Modifications/Deletions Table A-1. Document Revision HistoryImportant Notice