Texas Instruments TMS320C642x DSP Logical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram

Page 23

www.ti.com

Peripheral Architecture

Table 9. Logical Address-to-DDR2 SDRAM Address Map for 32-Bit SDRAM

SDBCR Bit										Logical Address(1)
IBANK	PAGESIZE	31	30	29	28	27	26	25	24	23	22:16	15	14	13	12	11	10	9:2	1:0
0	0	-									nrb=13							ncb=8
1	0	-								nrb=13							nbb=1	ncb=8
2h	0	-							nrb=13							nbb=2		ncb=8
3h	0	-						nrb=13							nbb=3			ncb=8
0	1	-								nrb=13							ncb=9
1	1	-							nrb=13							nbb=1	ncb=9
2h	1	-						nrb=13							nbb=2		ncb=9
3h	1	-					nrb=13							nbb=3			ncb=9
0	2h	-							nrb=13							ncb=10
1	2h	-						nrb=13							nbb=1	ncb=10
2h	2h	-					nrb=13							nbb=2		ncb=10
3h	2h	-				nrb=13							nbb=3			ncb=10
0	3h	-						nrb=13							ncb=11
1	3h	-					nrb=13							nbb=1	ncb=11
2h	3h	-				nrb=13							nbb=2		ncb=11
3h	3h				nrb=13							nbb=3			ncb=11

(1)Legend: ncb = number of column address bits; nrb = number of row address bits; nbb = number of bank address bits.

Table 10. Logical Address-to-DDR2 SDRAM Address Map for 16-bit SDRAM

SDBCR Bit										Logical Address(1)
IBANK	PAGESIZE	31	30	29	28	27	26	25	24	23	22	21:15	14	13	12	11	10	9	8:1	0
0	0	-										nrb=13							ncb=8
1	0	-									nrb=13							nbb=1	ncb=8
2h	0	-								nrb=13							nbb=2		ncb=8
3h	0	-							nrb=13							nbb=3			ncb=8
0	1	-									nrb=13							ncb=9
1	1	-								nrb=13							nbb=1	ncb=9
2h	1	-							nrb=13							nbb=2		ncb=9
3h	1	-						nrb=13							nbb=3			ncb=9
0	2h	-								nrb=13							ncb=10
1	2h	-							nrb=13							nbb=1	ncb=10
2h	2h	-						nrb=13							nbb=2		ncb=10
3h	2h	-					nrb=13							nbb=3			ncb=10
0	3h	-							nrb=13							ncb=11
1	3h	-						nrb=13							nbb=1	ncb=11
2h	3h	-					nrb=13							nbb=2		ncb=11
3h	3h	-				nrb=13							nbb=3			ncb=11

(1)Legend: ncb = number of column address bits; nrb = number of row address bits; nbb = number of bank address bits.

SPRUEM4A–November 2007	DDR2 Memory Controller	23
Submit Documentation Feedback

Image 23

Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Purpose of the Peripheral FeaturesIndustry Standards Compliance Statement Functional Block DiagramSupported Use Case Statement Clock Source Clock Control3 DDR2 Memory Controller Internal Clock Domains Clock ConfigurationPLLC2 Configuration Memory MapPin Type Description Signal DescriptionsDDR2 Memory Controller Signal Descriptions Clock enable Active highProtocol Descriptions DDR2 Sdram CommandsTruth Table for DDR2 Sdram Commands Command FunctionRefresh Command Refresh ModeDeactivation Dcab and Deac Dcab CommandDeac Command Activation Actv Actv CommandDDR2 Read Command Read CommandDDR2 WRT Command Write WRT CommandDDR2 MRS and Emrs Command Mode Register Set MRS and EmrsAddressable Memory Ranges Memory Width and Byte AlignmentBit External Memory Endianness SupportBit Field Bit Value Bit Description Bank Configuration Register Fields for Address MappingAddress Mapping Logical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map for 32-Bit SdramLogical Address-to-DDR2 Sdram Address Map DDR2 Sdram Column, Row, and Bank Access DDR2 Memory Controller Fifo Description DDR2 Memory Controller InterfaceCommand Ordering and Scheduling, Advanced Concept Possible Race Condition Command StarvationUrgency Level Description Self-Refresh ModeRefresh Scheduling Refresh Urgency LevelsReset Signal Reset Source Reset ConsiderationsReset Sources Auto-Initialization Sequence VTP IO Buffer CalibrationDDR2 Memory Controller DDR2 Sdram Configuration by MRS CommandDDR2 Sdram Configuration by EMRS1 Command Initializing Configuration RegistersPeripheral Architecture DMA Event Support Power ManagementInterrupt Support Emulation Considerations Supported Use Cases Connecting the DDR2 Memory Controller to DDR2 MemoryConnecting DDR2 Memory Controller for 32-Bit Connection DDR2 Memory Refresh Specification Configuring Sdram Bank Configuration Register SdbcrSdram Bank Configuration Register Sdbcr Configuration Configuring Sdram Refresh Control Register SdrcrDDR2 Data Register Field Manual Data Manual Formula Configuring Sdram Timing Registers Sdtimr and SDTIMR2Sdram Timing Register Sdtimr Configuration Sdram Timing Register 2 SDTIMR2 ConfigurationRegister Field Name Description Configuring DDR PHY Control Register DdrphycrDDR PHY Control Register Ddrphycr Configuration DDR VTP Register Mode D63-32D31-0 Acronym Register DescriptionBit Field Sdram Status Register SdrstatSdram Status Register Sdrstat Field Descriptions Bit Field Value Description Sdram Bank Configuration Register SdbcrSdram Bank Configuration Register Sdbcr Field Descriptions Reserved Reserved. Always write a 0 to this bit Sdram Refresh Control Register Sdrcr Field Descriptions Sdram Refresh Control Register SdrcrSdram Timing Register Sdtimr Field Descriptions Sdram Timing Register SdtimrSdram Timing Register 2 SDTIMR2 Field Descriptions Sdram Timing Register 2 SDTIMR2Peripheral Bus Burst Priority Register Pbbpr Peripheral Bus Burst Priority Register PbbprInterrupt Raw Register IRR Field Descriptions Interrupt Raw Register IRRInterrupt Masked Register IMR Field Descriptions Interrupt Masked Register IMRInterrupt Mask Set Register Imsr Field Descriptions Interrupt Mask Set Register ImsrInterrupt Mask Clear Register Imcr Field Descriptions Interrupt Mask Clear Register ImcrDDR PHY Control Register Ddrphycr Field Descriptions DDR PHY Control Register DdrphycrVTP IO Control Register Vtpiocr Field Descriptions VTP IO Control Register VtpiocrDDR VTP Register Ddrvtpr Field Descriptions DDR VTP Enable Register DdrvtperDDR VTP Enable Register Ddrvtper Field Descriptions DDR VTP Register DdrvtprAdditions/Modifications/Deletions Table A-1. Document Revision HistoryImportant Notice