Texas Instruments TMS320C642x DSP manual Interrupt Masked Register IMR

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DDR2 Memory Controller Registers

4.8Interrupt Masked Register (IMR)

The interrupt masked register (IMR) displays the status of the interrupt when it is enabled. If the interrupt condition occurs and the corresponding bit in the interrupt mask set register (IMSR) is set, then the IMR bit is set. The IMR bit is not set if the interrupt is not enabled in IMSR. The IMR is shown in Figure 26 and described in Table 32.

Figure 26. Interrupt Masked Register (IMR)

31				16
	Reserved
	R-0
15	3	2	1	0
Reserved		LTM	Reserved
R-0		R/W1C-0		R-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing 0 has no effect); -n= value after reset

			Table 32. Interrupt Masked Register (IMR) Field Descriptions
Bit	Field	Value	Description
31-3	Reserved	0	Reserved
2	LTM		Line trap masked. Write a 1 to clear LTM and the LT bit in the interrupt raw register (IRR); a write of 0
			has no effect.
		0	A line trap condition has not occurred.
		1	Illegal memory access type (only set if the LTMSET bit in IMSR is set). See Section 2.14 for more
			details.
1-0	Reserved	0	Reserved

50	DDR2 Memory Controller	SPRUEM4A–November 2007
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Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Features Purpose of the PeripheralIndustry Standards Compliance Statement Functional Block DiagramSupported Use Case Statement Clock Control Clock SourceMemory Map Clock ConfigurationPLLC2 Configuration 3 DDR2 Memory Controller Internal Clock DomainsClock enable Active high Signal DescriptionsDDR2 Memory Controller Signal Descriptions Pin Type DescriptionCommand Function DDR2 Sdram CommandsTruth Table for DDR2 Sdram Commands Protocol DescriptionsRefresh Mode Refresh CommandDcab Command Deactivation Dcab and DeacDeac Command Actv Command Activation ActvRead Command DDR2 Read CommandWrite WRT Command DDR2 WRT CommandMode Register Set MRS and Emrs DDR2 MRS and Emrs CommandMemory Width and Byte Alignment Addressable Memory RangesEndianness Support Bit External MemoryBit Field Bit Value Bit Description Bank Configuration Register Fields for Address MappingAddress Mapping Logical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram Logical Address-to-DDR2 Sdram Address Map for 16-bit SdramLogical Address-to-DDR2 Sdram Address Map DDR2 Sdram Column, Row, and Bank Access DDR2 Memory Controller Interface DDR2 Memory Controller Fifo DescriptionCommand Ordering and Scheduling, Advanced Concept Command Starvation Possible Race ConditionRefresh Urgency Levels Self-Refresh ModeRefresh Scheduling Urgency Level DescriptionReset Signal Reset Source Reset ConsiderationsReset Sources VTP IO Buffer Calibration Auto-Initialization SequenceInitializing Configuration Registers DDR2 Sdram Configuration by MRS CommandDDR2 Sdram Configuration by EMRS1 Command DDR2 Memory ControllerPeripheral Architecture DMA Event Support Power ManagementInterrupt Support Emulation Considerations Connecting the DDR2 Memory Controller to DDR2 Memory Supported Use CasesConnecting DDR2 Memory Controller for 32-Bit Connection Configuring Sdram Refresh Control Register Sdrcr Configuring Sdram Bank Configuration Register SdbcrSdram Bank Configuration Register Sdbcr Configuration DDR2 Memory Refresh SpecificationSdram Timing Register 2 SDTIMR2 Configuration Configuring Sdram Timing Registers Sdtimr and SDTIMR2Sdram Timing Register Sdtimr Configuration DDR2 Data Register Field Manual Data Manual FormulaRegister Field Name Description Configuring DDR PHY Control Register DdrphycrDDR PHY Control Register Ddrphycr Configuration Acronym Register Description Mode D63-32D31-0 DDR VTP RegisterBit Field Sdram Status Register SdrstatSdram Status Register Sdrstat Field Descriptions Bit Field Value Description Sdram Bank Configuration Register SdbcrSdram Bank Configuration Register Sdbcr Field Descriptions Reserved Reserved. Always write a 0 to this bit Sdram Refresh Control Register Sdrcr Sdram Refresh Control Register Sdrcr Field DescriptionsSdram Timing Register Sdtimr Sdram Timing Register Sdtimr Field DescriptionsSdram Timing Register 2 SDTIMR2 Sdram Timing Register 2 SDTIMR2 Field DescriptionsPeripheral Bus Burst Priority Register Pbbpr Peripheral Bus Burst Priority Register PbbprInterrupt Raw Register IRR Interrupt Raw Register IRR Field DescriptionsInterrupt Masked Register IMR Interrupt Masked Register IMR Field DescriptionsInterrupt Mask Set Register Imsr Interrupt Mask Set Register Imsr Field DescriptionsInterrupt Mask Clear Register Imcr Interrupt Mask Clear Register Imcr Field DescriptionsDDR PHY Control Register Ddrphycr DDR PHY Control Register Ddrphycr Field DescriptionsVTP IO Control Register Vtpiocr VTP IO Control Register Vtpiocr Field DescriptionsDDR VTP Register Ddrvtpr DDR VTP Enable Register DdrvtperDDR VTP Enable Register Ddrvtper Field Descriptions DDR VTP Register Ddrvtpr Field DescriptionsTable A-1. Document Revision History Additions/Modifications/DeletionsImportant Notice