Texas Instruments TMS320C642x DSP manual DDR2 Memory Controller Interface

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Peripheral Architecture

2.8DDR2 Memory Controller Interface

To move data efficiently from on-chip resources to external DDR2 SDRAM memory, the DDR2 memory controller makes use of a command FIFO, a write FIFO, a read FIFO, and command and data schedulers. Table 11 describes the purpose of each FIFO.

Figure 14 shows the block diagram of the DDR2 memory controller FIFOs. Commands, write data, and read data arrive at the DDR2 memory controller parallel to each other. The same peripheral bus is used to write and read data from external memory as well as internal memory-mapped registers.

Table 11. DDR2 Memory Controller FIFO Description

FIFO	Description	Depth (64-bit doublewords)
Command	Stores all commands coming from on-chip requestors	7
Write	Stores write data coming from on-chip requestors to memory	11
Read	Stores read data coming from memory to on-chip requestors	17

Figure 14. DDR2 Memory Controller FIFO Block Diagram

Command FIFO	Command/Data	Command
	Scheduler	to Memory
Write FIFO
		Write Data
		to Memory
Read FIFO
		Read Data
		from
		Memory
	Registers
Command
Data

26 DDR2 Memory Controller SPRUEM4A–November 2007

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