Texas Instruments TMS320C642x DSP manual Emulation Considerations

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Peripheral Architecture

2.16.1DDR2 Memory Controller Clock Stop Procedure

CAUTION

The following clock stop procedures are preliminary and are documented to reflect the intended-use cases. These clock stop procedures may change at a future date.

Note: If an access occurs to the DDR2 memory controller after completing steps 1-5, the DLL will wake up and lock, then the MCLK will turn on and the access will be performed. Following step 6, all DDR2 accesses are disabled until the DDR2 memory controller is enabled again through the LPSC.

To achieve maximum power savings VCLK, MCLK, X2_CLK, DDR_CLK, and DDR_CLK should be gated off, as well as the DDR2 memory controller DLL powered down. Perform the following procedure when shutting down clocks to achieve maximum power savings:

1.Allow software to complete the desired DDR2 transfers.

2.Set the SR bit in the DDR2 SDRAM refresh control register (SDRCR). The DDR2 memory controller will complete any outstanding accesses and backlogged refresh cycles and then place the external DDR2 memory in self-refresh mode.

3.Set the MCLKSTOPEN bit in SDRCR. This enables the DDR2 memory controller to shut off the MCLK.

4.Set the DLLPWRDN bit in the DDR PHY control register (DDRPHYCR) to 1 to power down the DDR2 memory controller DLL.

5.Poll the PHYRDY bit in the SDRAM status register (SDRSTAT) to be a logic-low indicating that the MCLK has been stopped and the DLL is powered down.

6.Program DDR2 memory controller LPSC to disable VCLK.

7.Program PLLC2 registers to stop PLL2_SYSCLK1 which disables X2_CLK of the DDR2 memory controller, as well as DDR_CLK and DDR_CLK.

To turn clocks back on:

1.Program PLLC2 registers to start PLL2_SYSCLK1 which sources X2_CLK of the DDR2 memory controller.

2.Once PLL2_SYSCLK1 is stable, program the DDR2 memory controller LPSC to enable VCLK.

3.Clear the MCLKSTOPEN bit in the DDR2 SDRAM refresh control register (SDRCR) to 0.

4.Clear the DLLPWRDN bit in the DDR PHY control register (DDRPHYCR) to 0 to power up the DDR2 memory controller DLL.

5.Perform a soft reset of the DDR2 memory controller via the PSC using the following procedure. See the TMS320C642x DSP Power and Sleep Controller (PSC) User's Guide (SPRUEN8) for details on how to program the PSC.

a.To put the DDR2 memory controller into soft reset, program the PSC to place the DDR2 memory controller into the SyncReset state.

b.To take the DDR2 memory controller out of soft reset, program the PSC to place the DDR2 memory controller into the Enable state.

6.Clear the SR bit in SDRCR to 0.

2.17Emulation Considerations

The DDR2 memory controller will remain fully functional during emulation halts to allow emulation access to external memory.

SPRUEM4A–November 2007

DDR2 Memory Controller

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Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Purpose of the Peripheral FeaturesIndustry Standards Compliance Statement Functional Block DiagramSupported Use Case Statement Clock Source Clock Control3 DDR2 Memory Controller Internal Clock Domains Clock ConfigurationPLLC2 Configuration Memory MapPin Type Description Signal DescriptionsDDR2 Memory Controller Signal Descriptions Clock enable Active highProtocol Descriptions DDR2 Sdram CommandsTruth Table for DDR2 Sdram Commands Command FunctionRefresh Command Refresh ModeDeactivation Dcab and Deac Dcab CommandDeac Command Activation Actv Actv CommandDDR2 Read Command Read CommandDDR2 WRT Command Write WRT CommandDDR2 MRS and Emrs Command Mode Register Set MRS and EmrsAddressable Memory Ranges Memory Width and Byte AlignmentBit External Memory Endianness SupportBit Field Bit Value Bit Description Bank Configuration Register Fields for Address MappingAddress Mapping Logical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map for 32-Bit SdramLogical Address-to-DDR2 Sdram Address Map DDR2 Sdram Column, Row, and Bank Access DDR2 Memory Controller Fifo Description DDR2 Memory Controller InterfaceCommand Ordering and Scheduling, Advanced Concept Possible Race Condition Command StarvationUrgency Level Description Self-Refresh ModeRefresh Scheduling Refresh Urgency LevelsReset Signal Reset Source Reset ConsiderationsReset Sources Auto-Initialization Sequence VTP IO Buffer CalibrationDDR2 Memory Controller DDR2 Sdram Configuration by MRS CommandDDR2 Sdram Configuration by EMRS1 Command Initializing Configuration RegistersPeripheral Architecture DMA Event Support Power ManagementInterrupt Support Emulation Considerations Supported Use Cases Connecting the DDR2 Memory Controller to DDR2 MemoryConnecting DDR2 Memory Controller for 32-Bit Connection DDR2 Memory Refresh Specification Configuring Sdram Bank Configuration Register SdbcrSdram Bank Configuration Register Sdbcr Configuration Configuring Sdram Refresh Control Register SdrcrDDR2 Data Register Field Manual Data Manual Formula Configuring Sdram Timing Registers Sdtimr and SDTIMR2Sdram Timing Register Sdtimr Configuration Sdram Timing Register 2 SDTIMR2 ConfigurationRegister Field Name Description Configuring DDR PHY Control Register DdrphycrDDR PHY Control Register Ddrphycr Configuration DDR VTP Register Mode D63-32D31-0 Acronym Register DescriptionBit Field Sdram Status Register SdrstatSdram Status Register Sdrstat Field Descriptions Bit Field Value Description Sdram Bank Configuration Register SdbcrSdram Bank Configuration Register Sdbcr Field Descriptions Reserved Reserved. Always write a 0 to this bit Sdram Refresh Control Register Sdrcr Field Descriptions Sdram Refresh Control Register SdrcrSdram Timing Register Sdtimr Field Descriptions Sdram Timing Register SdtimrSdram Timing Register 2 SDTIMR2 Field Descriptions Sdram Timing Register 2 SDTIMR2Peripheral Bus Burst Priority Register Pbbpr Peripheral Bus Burst Priority Register PbbprInterrupt Raw Register IRR Field Descriptions Interrupt Raw Register IRRInterrupt Masked Register IMR Field Descriptions Interrupt Masked Register IMRInterrupt Mask Set Register Imsr Field Descriptions Interrupt Mask Set Register ImsrInterrupt Mask Clear Register Imcr Field Descriptions Interrupt Mask Clear Register ImcrDDR PHY Control Register Ddrphycr Field Descriptions DDR PHY Control Register DdrphycrVTP IO Control Register Vtpiocr Field Descriptions VTP IO Control Register VtpiocrDDR VTP Register Ddrvtpr Field Descriptions DDR VTP Enable Register DdrvtperDDR VTP Enable Register Ddrvtper Field Descriptions DDR VTP Register DdrvtprAdditions/Modifications/Deletions Table A-1. Document Revision HistoryImportant Notice
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