Texas Instruments TMS320C642x DSP manual DDR PHY Control Register Ddrphycr

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DDR2 Memory Controller Registers

4.11 DDR PHY Control Register (DDRPHYCR)

The DDR PHY control register (DDRPHYCR) configures the DDR2 memory controller DLL for operation and determines whether the DLL is in reset, whether it is powered up, and the read latency. The DDRPHYCR is shown in Figure 29 and described in Table 35.

Figure 29. DDR PHY Control Register (DDRPHYCR)

31						16
	Reserved
	R/W-5000h
15	6	5	4	3	2	0
Reserved		DLLRESET	DLLPWRDN	Rsvd		READLAT
R/W-190h		R/W-0	R/W-1	R-1		R/W-7h

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 35. DDR PHY Control Register (DDRPHYCR) Field Descriptions

Bit	Field	Value	Description
31-16	Reserved	5000h	Reserved. Always write 5000h to these bits.
15-6	Reserved	190h	Reserved. Always write 190h to these bits.
5	DLLRESET		Reset DLL.
		0	DLL is out of reset.
		1	Places the DLL in reset.
4	DLLPWRDN		Power down DLL.
		0	DLL is powered up.
		1	DLL is powered down, if DLLPWRDN and the SR bit and MCLKSTOPEN bit in the SDRAM
			refresh control register (SDRCR) are set to 1.
3	Reserved	1	Reserved
2-0	READLAT	0-7h	Read latency. Read latency is equal to CAS latency plus round trip board delay for data
			minus 1. The maximum value of read latency that is supported is CAS latency plus 3. The
			minimum read latency value that is supported is CAS latency plus 1. The read latency value
			is defined in number of MCLK/DDR_CLK cycles.

SPRUEM4A–November 2007	DDR2 Memory Controller	53
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Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Purpose of the Peripheral FeaturesIndustry Standards Compliance Statement Functional Block DiagramSupported Use Case Statement Clock Source Clock ControlPLLC2 Configuration Clock ConfigurationMemory Map 3 DDR2 Memory Controller Internal Clock DomainsDDR2 Memory Controller Signal Descriptions Signal DescriptionsClock enable Active high Pin Type DescriptionTruth Table for DDR2 Sdram Commands DDR2 Sdram CommandsCommand Function Protocol DescriptionsRefresh Command Refresh ModeDeactivation Dcab and Deac Dcab CommandDeac Command Activation Actv Actv CommandDDR2 Read Command Read CommandDDR2 WRT Command Write WRT CommandDDR2 MRS and Emrs Command Mode Register Set MRS and EmrsAddressable Memory Ranges Memory Width and Byte AlignmentBit External Memory Endianness SupportBit Field Bit Value Bit Description Bank Configuration Register Fields for Address MappingAddress Mapping Logical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map for 32-Bit SdramLogical Address-to-DDR2 Sdram Address Map DDR2 Sdram Column, Row, and Bank Access DDR2 Memory Controller Fifo Description DDR2 Memory Controller InterfaceCommand Ordering and Scheduling, Advanced Concept Possible Race Condition Command StarvationRefresh Scheduling Self-Refresh ModeRefresh Urgency Levels Urgency Level DescriptionReset Signal Reset Source Reset ConsiderationsReset Sources Auto-Initialization Sequence VTP IO Buffer CalibrationDDR2 Sdram Configuration by EMRS1 Command DDR2 Sdram Configuration by MRS CommandInitializing Configuration Registers DDR2 Memory ControllerPeripheral Architecture DMA Event Support Power ManagementInterrupt Support Emulation Considerations Supported Use Cases Connecting the DDR2 Memory Controller to DDR2 MemoryConnecting DDR2 Memory Controller for 32-Bit Connection Sdram Bank Configuration Register Sdbcr Configuration Configuring Sdram Bank Configuration Register SdbcrConfiguring Sdram Refresh Control Register Sdrcr DDR2 Memory Refresh SpecificationSdram Timing Register Sdtimr Configuration Configuring Sdram Timing Registers Sdtimr and SDTIMR2Sdram Timing Register 2 SDTIMR2 Configuration DDR2 Data Register Field Manual Data Manual FormulaRegister Field Name Description Configuring DDR PHY Control Register DdrphycrDDR PHY Control Register Ddrphycr Configuration D31-0 Mode D63-32Acronym Register Description DDR VTP RegisterBit Field Sdram Status Register SdrstatSdram Status Register Sdrstat Field Descriptions Bit Field Value Description Sdram Bank Configuration Register SdbcrSdram Bank Configuration Register Sdbcr Field Descriptions Reserved Reserved. Always write a 0 to this bit Sdram Refresh Control Register Sdrcr Field Descriptions Sdram Refresh Control Register SdrcrSdram Timing Register Sdtimr Field Descriptions Sdram Timing Register SdtimrSdram Timing Register 2 SDTIMR2 Field Descriptions Sdram Timing Register 2 SDTIMR2Peripheral Bus Burst Priority Register Pbbpr Peripheral Bus Burst Priority Register PbbprInterrupt Raw Register IRR Field Descriptions Interrupt Raw Register IRRInterrupt Masked Register IMR Field Descriptions Interrupt Masked Register IMRInterrupt Mask Set Register Imsr Field Descriptions Interrupt Mask Set Register ImsrInterrupt Mask Clear Register Imcr Field Descriptions Interrupt Mask Clear Register ImcrDDR PHY Control Register Ddrphycr Field Descriptions DDR PHY Control Register DdrphycrVTP IO Control Register Vtpiocr Field Descriptions VTP IO Control Register VtpiocrDDR VTP Enable Register Ddrvtper Field Descriptions DDR VTP Enable Register DdrvtperDDR VTP Register Ddrvtpr DDR VTP Register Ddrvtpr Field DescriptionsAdditions/Modifications/Deletions Table A-1. Document Revision HistoryImportant Notice