Texas Instruments
TMS320C642x DSP
manual
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Functional Block Diagram
Signal Descriptions
Clock Configuration
Reset Considerations
DDR2 Sdram Commands
Power Management
Features
Refresh Mode
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2
SPRUEM4A–November
2007
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Contents
Users Guide
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Contents
List of Figures
List of Tables
Read This First
Features
Purpose of the Peripheral
Industry Standards Compliance Statement
Functional Block Diagram
Supported Use Case Statement
Clock Control
Clock Source
Memory Map
Clock Configuration
PLLC2 Configuration
3 DDR2 Memory Controller Internal Clock Domains
Clock enable Active high
Signal Descriptions
DDR2 Memory Controller Signal Descriptions
Pin Type Description
Command Function
DDR2 Sdram Commands
Truth Table for DDR2 Sdram Commands
Protocol Descriptions
Refresh Mode
Refresh Command
Dcab Command
Deactivation Dcab and Deac
Deac Command
Actv Command
Activation Actv
Read Command
DDR2 Read Command
Write WRT Command
DDR2 WRT Command
Mode Register Set MRS and Emrs
DDR2 MRS and Emrs Command
Memory Width and Byte Alignment
Addressable Memory Ranges
Endianness Support
Bit External Memory
Bit Field Bit Value Bit Description
Bank Configuration Register Fields for Address Mapping
Address Mapping
Logical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram
Logical Address-to-DDR2 Sdram Address Map for 16-bit Sdram
Logical Address-to-DDR2 Sdram Address Map
DDR2 Sdram Column, Row, and Bank Access
DDR2 Memory Controller Interface
DDR2 Memory Controller Fifo Description
Command Ordering and Scheduling, Advanced Concept
Command Starvation
Possible Race Condition
Refresh Urgency Levels
Self-Refresh Mode
Refresh Scheduling
Urgency Level Description
Reset Signal Reset Source
Reset Considerations
Reset Sources
VTP IO Buffer Calibration
Auto-Initialization Sequence
Initializing Configuration Registers
DDR2 Sdram Configuration by MRS Command
DDR2 Sdram Configuration by EMRS1 Command
DDR2 Memory Controller
Peripheral Architecture
DMA Event Support
Power Management
Interrupt Support
Emulation Considerations
Connecting the DDR2 Memory Controller to DDR2 Memory
Supported Use Cases
Connecting DDR2 Memory Controller for 32-Bit Connection
Configuring Sdram Refresh Control Register Sdrcr
Configuring Sdram Bank Configuration Register Sdbcr
Sdram Bank Configuration Register Sdbcr Configuration
DDR2 Memory Refresh Specification
Sdram Timing Register 2 SDTIMR2 Configuration
Configuring Sdram Timing Registers Sdtimr and SDTIMR2
Sdram Timing Register Sdtimr Configuration
DDR2 Data Register Field Manual Data Manual Formula
Register Field Name Description
Configuring DDR PHY Control Register Ddrphycr
DDR PHY Control Register Ddrphycr Configuration
Acronym Register Description
Mode D63-32
D31-0
DDR VTP Register
Bit Field
Sdram Status Register Sdrstat
Sdram Status Register Sdrstat Field Descriptions
Bit Field Value Description
Sdram Bank Configuration Register Sdbcr
Sdram Bank Configuration Register Sdbcr Field Descriptions
Reserved Reserved. Always write a 0 to this bit
Sdram Refresh Control Register Sdrcr
Sdram Refresh Control Register Sdrcr Field Descriptions
Sdram Timing Register Sdtimr
Sdram Timing Register Sdtimr Field Descriptions
Sdram Timing Register 2 SDTIMR2
Sdram Timing Register 2 SDTIMR2 Field Descriptions
Peripheral Bus Burst Priority Register Pbbpr
Peripheral Bus Burst Priority Register Pbbpr
Interrupt Raw Register IRR
Interrupt Raw Register IRR Field Descriptions
Interrupt Masked Register IMR
Interrupt Masked Register IMR Field Descriptions
Interrupt Mask Set Register Imsr
Interrupt Mask Set Register Imsr Field Descriptions
Interrupt Mask Clear Register Imcr
Interrupt Mask Clear Register Imcr Field Descriptions
DDR PHY Control Register Ddrphycr
DDR PHY Control Register Ddrphycr Field Descriptions
VTP IO Control Register Vtpiocr
VTP IO Control Register Vtpiocr Field Descriptions
DDR VTP Register Ddrvtpr
DDR VTP Enable Register Ddrvtper
DDR VTP Enable Register Ddrvtper Field Descriptions
DDR VTP Register Ddrvtpr Field Descriptions
Table A-1. Document Revision History
Additions/Modifications/Deletions
Important Notice
Related pages
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