Texas Instruments TMS320C642x DSP manual VTP IO Control Register Vtpiocr

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DDR2 Memory Controller Registers

4.12 VTP IO Control Register (VTPIOCR)

The VTP IO control register (VTPIOCR) is used to control the calibration of the DDR2 memory controller IOs with respect to voltage, temperature, and process (VTP). The voltage, temperature, and process information is used to control the IO's output impedance. The VTPIOCR is shown in Figure 30 and described in Table 36.

Figure 30. VTP IO Control Register (VTPIOCR)

31									16
						Reserved
						R-0
15	14	13	12	11	10	9	5	4	0
RECAL	Rsvd	EN	Reserved		Rsvd	PCH			NCH
R/W-0	R/W-0	R/W-0	R/W-0		R-0	R/W-0			R/W-1Fh

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 36. VTP IO Control Register (VTPIOCR) Field Descriptions

Bit	Field	Value	Description
31-16	Reserved	0	Reserved
15	RECAL		Start VTP IO calibration.
		0	Normal operation
		1	Transition from 0 to 1 starts VTP IO calibration.
14	Reserved	0	Reserved. Always write a 0 to this bit.
13	EN		VTP enable.
		0	VTP IO calibration is disabled.
		1	VTP IO calibration is enabled.
12-11	Reserved	0	Reserved. Always write a 0 to this bit.
10	Reserved	0	Reserved
9-5	PCH	0-1Fh	P channel value. This value is driven to the IO to calibrate the impedance of the IO. The value of PCH
			is determined by reading the DDR VTP register (DDRVTPR). See Section 4.13 for details.
4-0	NCH	0-1Fh	N channel value. This value is driven to the IO to calibrate the impedance of the IO. The value of NCH
			is determined by reading the DDR VTP register (DDRVTPR). See Section 4.13 for details.

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DDR2 Memory Controller

SPRUEM4A–November 2007

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Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Features Purpose of the PeripheralFunctional Block Diagram Supported Use Case StatementIndustry Standards Compliance Statement Clock Control Clock SourceMemory Map Clock ConfigurationPLLC2 Configuration 3 DDR2 Memory Controller Internal Clock DomainsClock enable Active high Signal DescriptionsDDR2 Memory Controller Signal Descriptions Pin Type DescriptionCommand Function DDR2 Sdram CommandsTruth Table for DDR2 Sdram Commands Protocol DescriptionsRefresh Mode Refresh CommandDcab Command Deactivation Dcab and DeacDeac Command Actv Command Activation ActvRead Command DDR2 Read CommandWrite WRT Command DDR2 WRT CommandMode Register Set MRS and Emrs DDR2 MRS and Emrs CommandMemory Width and Byte Alignment Addressable Memory RangesEndianness Support Bit External MemoryBank Configuration Register Fields for Address Mapping Address MappingBit Field Bit Value Bit Description Logical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram Logical Address-to-DDR2 Sdram Address Map for 16-bit SdramLogical Address-to-DDR2 Sdram Address Map DDR2 Sdram Column, Row, and Bank Access DDR2 Memory Controller Interface DDR2 Memory Controller Fifo DescriptionCommand Ordering and Scheduling, Advanced Concept Command Starvation Possible Race ConditionRefresh Urgency Levels Self-Refresh ModeRefresh Scheduling Urgency Level DescriptionReset Considerations Reset SourcesReset Signal Reset Source VTP IO Buffer Calibration Auto-Initialization SequenceInitializing Configuration Registers DDR2 Sdram Configuration by MRS CommandDDR2 Sdram Configuration by EMRS1 Command DDR2 Memory ControllerPeripheral Architecture Power Management Interrupt SupportDMA Event Support Emulation Considerations Connecting the DDR2 Memory Controller to DDR2 Memory Supported Use CasesConnecting DDR2 Memory Controller for 32-Bit Connection Configuring Sdram Refresh Control Register Sdrcr Configuring Sdram Bank Configuration Register SdbcrSdram Bank Configuration Register Sdbcr Configuration DDR2 Memory Refresh SpecificationSdram Timing Register 2 SDTIMR2 Configuration Configuring Sdram Timing Registers Sdtimr and SDTIMR2Sdram Timing Register Sdtimr Configuration DDR2 Data Register Field Manual Data Manual FormulaConfiguring DDR PHY Control Register Ddrphycr DDR PHY Control Register Ddrphycr ConfigurationRegister Field Name Description Acronym Register Description Mode D63-32D31-0 DDR VTP RegisterSdram Status Register Sdrstat Sdram Status Register Sdrstat Field DescriptionsBit Field Sdram Bank Configuration Register Sdbcr Sdram Bank Configuration Register Sdbcr Field DescriptionsBit Field Value Description Reserved Reserved. Always write a 0 to this bit Sdram Refresh Control Register Sdrcr Sdram Refresh Control Register Sdrcr Field DescriptionsSdram Timing Register Sdtimr Sdram Timing Register Sdtimr Field DescriptionsSdram Timing Register 2 SDTIMR2 Sdram Timing Register 2 SDTIMR2 Field DescriptionsPeripheral Bus Burst Priority Register Pbbpr Peripheral Bus Burst Priority Register PbbprInterrupt Raw Register IRR Interrupt Raw Register IRR Field DescriptionsInterrupt Masked Register IMR Interrupt Masked Register IMR Field DescriptionsInterrupt Mask Set Register Imsr Interrupt Mask Set Register Imsr Field DescriptionsInterrupt Mask Clear Register Imcr Interrupt Mask Clear Register Imcr Field DescriptionsDDR PHY Control Register Ddrphycr DDR PHY Control Register Ddrphycr Field DescriptionsVTP IO Control Register Vtpiocr VTP IO Control Register Vtpiocr Field DescriptionsDDR VTP Register Ddrvtpr DDR VTP Enable Register DdrvtperDDR VTP Enable Register Ddrvtper Field Descriptions DDR VTP Register Ddrvtpr Field DescriptionsTable A-1. Document Revision History Additions/Modifications/DeletionsImportant Notice