Texas Instruments TMS320C642x DSP DDR VTP Register Ddrvtpr, DDR VTP Enable Register Ddrvtper

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DDR2 Memory Controller Registers

4.13 DDR VTP Register (DDRVTPR)

The DDR VTP register (DDRVTPR) is used in conjunction with the VTP IO control register (VTPIOCR) to calibrate the output impedance of the DDR2 memory controller IOs with respect to voltage, temperature, and process. Following the calibration sequence, DDRVTPR contains the information needed to calibrate the impedance of the IO. Once the calibration sequence has completed, DDRVTPR should be read and the data written to the PCH and NCH fields in VTPIOCR. The DDRVTPR is shown in Figure 31 and described in Table 37.

Figure 31. DDR VTP Register (DDRVTPR)

31					16
		Reserved
		R-0
15	10	9	5	4	0
Reserved		PCH			NCH
R-0		R-0			R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

			Table 37. DDR VTP Register (DDRVTPR) Field Descriptions
Bit	Field	Value	Description
31-10	Reserved	0	Reserved.
9-5	PCH	0-1Fh	P channel value for IO impedance calibration. Following the VTP calibration sequence, this value should
			be read and written to the PCH field in the VTP IO control register (VTPIOCR).
4-0	NCH	0-1Fh	N channel value for IO impedance calibration. Following the VTP calibration sequence, this value
			should be read and written to the NCH field in the VTP IO control register (VTPIOCR).

4.14 DDR VTP Enable Register (DDRVTPER)

The DDR VTP enable register (DDRVTPER) is used to enable/disable accesses to the DDR VTP register (DDRVTPR). Writing a value of 1 to DDRVTPER enables accesses to DDRVTPR and writing a value of 0 disables accesses to DDRVTPR. The DDRVTPER is shown in Figure 32 and described in Table 38.

Figure 32. DDR VTP Enable Register (DDRVTPER)

31		16
Reserved
R-0
15	1	0
Reserved		EN
R-0		R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 38. DDR VTP Enable Register (DDRVTPER) Field Descriptions

Bit	Field	Value	Description
31-1	Reserved	0	Reserved. Always write 0 to these bits.
0	EN		DDRVTPR access enable.
		0	Access to DDRVTPR is disabled.
		1	Access to DDRVTPR is enabled.

SPRUEM4A–November 2007	DDR2 Memory Controller	55
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Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Purpose of the Peripheral FeaturesSupported Use Case Statement Functional Block DiagramIndustry Standards Compliance Statement Clock Source Clock Control3 DDR2 Memory Controller Internal Clock Domains Clock ConfigurationPLLC2 Configuration Memory MapPin Type Description Signal DescriptionsDDR2 Memory Controller Signal Descriptions Clock enable Active highProtocol Descriptions DDR2 Sdram CommandsTruth Table for DDR2 Sdram Commands Command FunctionRefresh Command Refresh ModeDeactivation Dcab and Deac Dcab CommandDeac Command Activation Actv Actv CommandDDR2 Read Command Read CommandDDR2 WRT Command Write WRT CommandDDR2 MRS and Emrs Command Mode Register Set MRS and EmrsAddressable Memory Ranges Memory Width and Byte AlignmentBit External Memory Endianness SupportAddress Mapping Bank Configuration Register Fields for Address MappingBit Field Bit Value Bit Description Logical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map for 32-Bit SdramLogical Address-to-DDR2 Sdram Address Map DDR2 Sdram Column, Row, and Bank Access DDR2 Memory Controller Fifo Description DDR2 Memory Controller InterfaceCommand Ordering and Scheduling, Advanced Concept Possible Race Condition Command StarvationUrgency Level Description Self-Refresh ModeRefresh Scheduling Refresh Urgency LevelsReset Sources Reset ConsiderationsReset Signal Reset Source Auto-Initialization Sequence VTP IO Buffer CalibrationDDR2 Memory Controller DDR2 Sdram Configuration by MRS CommandDDR2 Sdram Configuration by EMRS1 Command Initializing Configuration RegistersPeripheral Architecture Interrupt Support Power ManagementDMA Event Support Emulation Considerations Supported Use Cases Connecting the DDR2 Memory Controller to DDR2 MemoryConnecting DDR2 Memory Controller for 32-Bit Connection DDR2 Memory Refresh Specification Configuring Sdram Bank Configuration Register SdbcrSdram Bank Configuration Register Sdbcr Configuration Configuring Sdram Refresh Control Register SdrcrDDR2 Data Register Field Manual Data Manual Formula Configuring Sdram Timing Registers Sdtimr and SDTIMR2Sdram Timing Register Sdtimr Configuration Sdram Timing Register 2 SDTIMR2 ConfigurationDDR PHY Control Register Ddrphycr Configuration Configuring DDR PHY Control Register DdrphycrRegister Field Name Description DDR VTP Register Mode D63-32D31-0 Acronym Register DescriptionSdram Status Register Sdrstat Field Descriptions Sdram Status Register SdrstatBit Field Sdram Bank Configuration Register Sdbcr Field Descriptions Sdram Bank Configuration Register SdbcrBit Field Value Description Reserved Reserved. Always write a 0 to this bit Sdram Refresh Control Register Sdrcr Field Descriptions Sdram Refresh Control Register SdrcrSdram Timing Register Sdtimr Field Descriptions Sdram Timing Register SdtimrSdram Timing Register 2 SDTIMR2 Field Descriptions Sdram Timing Register 2 SDTIMR2Peripheral Bus Burst Priority Register Pbbpr Peripheral Bus Burst Priority Register PbbprInterrupt Raw Register IRR Field Descriptions Interrupt Raw Register IRRInterrupt Masked Register IMR Field Descriptions Interrupt Masked Register IMRInterrupt Mask Set Register Imsr Field Descriptions Interrupt Mask Set Register ImsrInterrupt Mask Clear Register Imcr Field Descriptions Interrupt Mask Clear Register ImcrDDR PHY Control Register Ddrphycr Field Descriptions DDR PHY Control Register DdrphycrVTP IO Control Register Vtpiocr Field Descriptions VTP IO Control Register VtpiocrDDR VTP Register Ddrvtpr Field Descriptions DDR VTP Enable Register DdrvtperDDR VTP Enable Register Ddrvtper Field Descriptions DDR VTP Register DdrvtprAdditions/Modifications/Deletions Table A-1. Document Revision HistoryImportant Notice