Texas Instruments TMS320C642x DSP manual Sdram Timing Register Sdtimr

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DDR2 Memory Controller Registers

4.4SDRAM Timing Register (SDTIMR)

The SDRAM timing register (SDTIMR) configures the DDR2 memory controller to meet many of the AC timing specification of the DDR2 memory. The SDTIMR register is programmable only when the TIMUNLOCK bit is set to 1 in the SDBCR. Note that DDR_CLK is equal to the period of the DDR_CLK signal. See the DDR2 memory data sheet for information on the appropriate values to program each field. The SDTIMR is shown in Figure 22 and described in Table 28.

Figure 22. SDRAM Timing Register (SDTIMR)

31

 

 

25

24

22

21

19

18

 

16

 

T_RFC

 

 

 

T_RP

 

T_RCD

 

T_WR

 

 

R/W-1Ah

 

 

 

R/W-5h

 

R/W-5h

 

R/W-3h

 

15

11

10

 

 

6

5

3

2

1

0

 

T_RAS

 

 

T_RC

 

 

T_RRD

Rsvd

T_WTR

 

R/W-9h

 

 

R/W-Eh

 

 

R/W-3h

R-0

R/W-3h

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 28. SDRAM Timing Register (SDTIMR) Field Descriptions

Bit

Field

Value

Description

31-25

T_RFC

0-7Fh

Specifies the minimum number of DDR_CLK cycles from a refresh or load mode command to a refresh

 

 

 

or activate command, minus 1. Corresponds to the trfc AC timing parameter in the DDR2 data sheet.

 

 

 

Calculate by:

 

 

 

T_RFC = (trfc/DDR_CLK period) - 1

24-22

T_RP

0-7h

Specifies the minimum number of DDR_CLK cycles from a precharge command to a refresh or activate

 

 

 

command, minus 1. Corresponds to the trp AC timing parameter in the DDR2 data sheet. Calculate by:

 

 

 

T_RP = (trp/DDR_CLK period) - 1

21-19

T_RCD

0-7h

Specifies the minimum number of DDR_CLK cycles from an activate command to a read or write

 

 

 

command, minus 1. Corresponds to the trcd AC timing parameter in the DDR2 data sheet. Calculate by:

 

 

 

T_RCD = (trcd/DDR_CLK period) - 1

18-16

T_WR

0-7h

Specifies the minimum number of DDR_CLK cycles from the last write transfer to a precharge

 

 

 

command, minus 1. Corresponds to the twr AC timing parameter in the DDR2 data sheet. Calculate by:

 

 

 

T_WR = (twr/DDR_CLK period) - 1

 

 

 

When the value of this field is changed from its previous value, the initialization sequence will begin.

15-11

T_RAS

0-1Fh

Specifies the minimum number of DDR_CLK cycles from an activate command to a precharge

 

 

 

command, minus 1. Corresponds to the tras AC timing parameter in the DDR2 data sheet. Calculate by:

 

 

 

T_RAS = (tras/DDR_CLK period) - 1

 

 

 

T_RAS must be greater than or equal to T_RCD.

10-6

T_RC

0-1Fh

Specifies the minimum number of DDR_CLK cycles from an activate command to an activate

 

 

 

command, minus 1. Corresponds to the trc AC timing parameter in the DDR2 data sheet. Calculate by:

 

 

 

T_RC = (trc/DDR_CLK period) - 1

5-3

T_RRD

0-7h

Specifies the minimum number of DDR_CLK cycles from an activate command to an activate command

 

 

 

in a different bank, minus 1. Corresponds to the trrd AC timing parameter in the DDR2 data sheet.

 

 

 

Calculate by:

 

 

 

T_RRD = (trrd/DDR_CLK period) - 1

 

 

 

Note: for an 8 bank DDR2 device this field must be equal to ((4 × tRRD) + (2 × tCK)) / (4 × tCK) - 1.

2

Reserved

0

Reserved

1-0

T_WTR

0-3h

Specifies the minimum number of DDR_CLK cycles from the last write to a read command, minus 1.

 

 

 

Corresponds to the twtr AC timing parameter in the DDR2 data sheet. Calculate by:

T_WTR = (twtr/DDR_CLK period) - 1

46

DDR2 Memory Controller

SPRUEM4A–November 2007

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Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Features Purpose of the PeripheralSupported Use Case Statement Functional Block DiagramIndustry Standards Compliance Statement Clock Control Clock SourceMemory Map Clock ConfigurationPLLC2 Configuration 3 DDR2 Memory Controller Internal Clock DomainsClock enable Active high Signal DescriptionsDDR2 Memory Controller Signal Descriptions Pin Type DescriptionCommand Function DDR2 Sdram CommandsTruth Table for DDR2 Sdram Commands Protocol DescriptionsRefresh Mode Refresh CommandDcab Command Deactivation Dcab and DeacDeac Command Actv Command Activation ActvRead Command DDR2 Read CommandWrite WRT Command DDR2 WRT CommandMode Register Set MRS and Emrs DDR2 MRS and Emrs CommandMemory Width and Byte Alignment Addressable Memory RangesEndianness Support Bit External MemoryAddress Mapping Bank Configuration Register Fields for Address MappingBit Field Bit Value Bit Description Logical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram Logical Address-to-DDR2 Sdram Address Map for 16-bit SdramLogical Address-to-DDR2 Sdram Address Map DDR2 Sdram Column, Row, and Bank Access DDR2 Memory Controller Interface DDR2 Memory Controller Fifo DescriptionCommand Ordering and Scheduling, Advanced Concept Command Starvation Possible Race ConditionRefresh Urgency Levels Self-Refresh ModeRefresh Scheduling Urgency Level DescriptionReset Sources Reset ConsiderationsReset Signal Reset Source VTP IO Buffer Calibration Auto-Initialization SequenceInitializing Configuration Registers DDR2 Sdram Configuration by MRS CommandDDR2 Sdram Configuration by EMRS1 Command DDR2 Memory ControllerPeripheral Architecture Interrupt Support Power ManagementDMA Event Support Emulation Considerations Connecting the DDR2 Memory Controller to DDR2 Memory Supported Use CasesConnecting DDR2 Memory Controller for 32-Bit Connection Configuring Sdram Refresh Control Register Sdrcr Configuring Sdram Bank Configuration Register SdbcrSdram Bank Configuration Register Sdbcr Configuration DDR2 Memory Refresh SpecificationSdram Timing Register 2 SDTIMR2 Configuration Configuring Sdram Timing Registers Sdtimr and SDTIMR2Sdram Timing Register Sdtimr Configuration DDR2 Data Register Field Manual Data Manual FormulaDDR PHY Control Register Ddrphycr Configuration Configuring DDR PHY Control Register DdrphycrRegister Field Name Description Acronym Register Description Mode D63-32D31-0 DDR VTP RegisterSdram Status Register Sdrstat Field Descriptions Sdram Status Register SdrstatBit Field Sdram Bank Configuration Register Sdbcr Field Descriptions Sdram Bank Configuration Register SdbcrBit Field Value Description Reserved Reserved. Always write a 0 to this bit Sdram Refresh Control Register Sdrcr Sdram Refresh Control Register Sdrcr Field DescriptionsSdram Timing Register Sdtimr Sdram Timing Register Sdtimr Field DescriptionsSdram Timing Register 2 SDTIMR2 Sdram Timing Register 2 SDTIMR2 Field DescriptionsPeripheral Bus Burst Priority Register Pbbpr Peripheral Bus Burst Priority Register PbbprInterrupt Raw Register IRR Interrupt Raw Register IRR Field DescriptionsInterrupt Masked Register IMR Interrupt Masked Register IMR Field DescriptionsInterrupt Mask Set Register Imsr Interrupt Mask Set Register Imsr Field DescriptionsInterrupt Mask Clear Register Imcr Interrupt Mask Clear Register Imcr Field DescriptionsDDR PHY Control Register Ddrphycr DDR PHY Control Register Ddrphycr Field DescriptionsVTP IO Control Register Vtpiocr VTP IO Control Register Vtpiocr Field DescriptionsDDR VTP Register Ddrvtpr DDR VTP Enable Register DdrvtperDDR VTP Enable Register Ddrvtper Field Descriptions DDR VTP Register Ddrvtpr Field DescriptionsTable A-1. Document Revision History Additions/Modifications/DeletionsImportant Notice
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