Texas Instruments TMS320C642x DSP manual VTP IO Buffer Calibration, Auto-Initialization Sequence

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Peripheral Architecture

2.12 VTP IO Buffer Calibration

The DDR2 memory controller is able to control the impedance of the output IO. This feature allows the DDR2 memory controller to tune the output impedance of the IO to match that of the PCB board. Control of the output impedance of the IO is an important feature because impedance matching reduces reflections, creating a cleaner board design. Calibrating the output impedance of the IO will also reduce the power consumption of the DDR2 memory controller. The calibration is performed with respect to voltage, temperature, and process (VTP). The VTP information obtained from the calibration is used to control the output impedance of the IO.

The impedance of the output IO is selected by the value of resistors connected to the DDR_ZN and DDR_ZP pins. The resistor should be chosen to be 4 times the desired impedance of the output IO. The DDR2 reference design requires the resistor values to be 200 ohms. This means that both the DDR_ZN and DDR_ZP pins must have a 200 ohm resistor connected to them. Figure 3 describes proper connection of the DDR_ZN and DDR_ZP pins.

To set the output impedance of the IO, calibration must be initiated by writing to the following memory-mapped registers:

∙VTP IO Control Register (VTPIOCR)

∙DDR VTP Register (DDRVTPR)

∙DDR VTP Enable Register (DDRVTPER)

The VTP IO control register is written to begin the calibration. Once the calibration is complete, the VTP information is stored in the DDR VTP register. The DDR VTP register should then be read, retrieving the VTP information, and the VTP information written to the VTP IO control register. The DDR VTP enable register is written to enable/disable access to the DDR VTP register. Steps 8-15 of the initialization procedure described in Section 2.13.2 shows the procedure that must be followed to perform VTP IO calibration.

Note: VTP IO calibration must be performed following device power up and device reset. If the DDR2 memory controller is reset via the Power and Sleep Controller (PSC) and the VTP input clock is disabled, accesses to the DDR2 memory controller will not complete. To re-enable accesses to the DDR2 memory controller, enable the VTP input clock and then perform the VTP calibration sequence again.

2.13 Auto-Initialization Sequence

The DDR2 SDRAM contains mode and extended mode registers that configure the DDR2 memory for operation. These registers control burst type, burst length, CAS latency, DLL enable/disable (on the DDR2 device), single-ended strobe, etc. The DDR2 memory controller programs the mode and extended mode registers of the DDR2 memory by issuing MRS and EMRS commands during the initialization sequence. The initialization sequence performed by the DDR2 memory controller is compliant with the JESDEC79-2A specification. The DDR2 memory controller performs an initialization sequence under the following conditions:

∙Following reset (rising edge of VRST or VCTL_RST)

∙Following a write to the DDRDRIVE bit field or the two least-significant bytes in the SDRAM bank configuration register (SDBCR)

During the initialization sequence, the DDR2 memory controller issues MRS and EMRS commands that configure the DDR2 SDRAM mode register and extended mode register 1 with the values described in Table 14 and Table 15. The DDR2 SDRAM extended mode registers 2 and 3 are configured with a value of 0h. At the end of the initialization sequence, the DDR2 memory controller performs an autorefresh cycle, leaving the DDR2 memory controller in an idle state with all banks deactivated.

When a reset occurs, the DDR2 memory controller immediately begins the initialization sequence. Under this condition, commands and data stored in the DDR2 memory controller FIFOs will be lost. However, when the initialization sequence is initiated by a write to the two least-significant bytes in SDBCR, data and commands stored in the DDR2 memory controller FIFOs will not be lost and the DDR2 memory controller will ensure read and write commands are completed before starting the initialization sequence.

SPRUEM4A–November 2007

DDR2 Memory Controller

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Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Purpose of the Peripheral FeaturesSupported Use Case Statement Functional Block DiagramIndustry Standards Compliance Statement Clock Source Clock Control3 DDR2 Memory Controller Internal Clock Domains Clock ConfigurationPLLC2 Configuration Memory MapPin Type Description Signal DescriptionsDDR2 Memory Controller Signal Descriptions Clock enable Active highProtocol Descriptions DDR2 Sdram CommandsTruth Table for DDR2 Sdram Commands Command FunctionRefresh Command Refresh ModeDeactivation Dcab and Deac Dcab CommandDeac Command Activation Actv Actv CommandDDR2 Read Command Read CommandDDR2 WRT Command Write WRT CommandDDR2 MRS and Emrs Command Mode Register Set MRS and EmrsAddressable Memory Ranges Memory Width and Byte AlignmentBit External Memory Endianness SupportAddress Mapping Bank Configuration Register Fields for Address MappingBit Field Bit Value Bit Description Logical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map for 32-Bit SdramLogical Address-to-DDR2 Sdram Address Map DDR2 Sdram Column, Row, and Bank Access DDR2 Memory Controller Fifo Description DDR2 Memory Controller InterfaceCommand Ordering and Scheduling, Advanced Concept Possible Race Condition Command StarvationUrgency Level Description Self-Refresh ModeRefresh Scheduling Refresh Urgency LevelsReset Sources Reset ConsiderationsReset Signal Reset Source Auto-Initialization Sequence VTP IO Buffer CalibrationDDR2 Memory Controller DDR2 Sdram Configuration by MRS CommandDDR2 Sdram Configuration by EMRS1 Command Initializing Configuration RegistersPeripheral Architecture Interrupt Support Power ManagementDMA Event Support Emulation Considerations Supported Use Cases Connecting the DDR2 Memory Controller to DDR2 MemoryConnecting DDR2 Memory Controller for 32-Bit Connection DDR2 Memory Refresh Specification Configuring Sdram Bank Configuration Register SdbcrSdram Bank Configuration Register Sdbcr Configuration Configuring Sdram Refresh Control Register SdrcrDDR2 Data Register Field Manual Data Manual Formula Configuring Sdram Timing Registers Sdtimr and SDTIMR2Sdram Timing Register Sdtimr Configuration Sdram Timing Register 2 SDTIMR2 ConfigurationDDR PHY Control Register Ddrphycr Configuration Configuring DDR PHY Control Register DdrphycrRegister Field Name Description DDR VTP Register Mode D63-32D31-0 Acronym Register DescriptionSdram Status Register Sdrstat Field Descriptions Sdram Status Register SdrstatBit Field Sdram Bank Configuration Register Sdbcr Field Descriptions Sdram Bank Configuration Register SdbcrBit Field Value Description Reserved Reserved. Always write a 0 to this bit Sdram Refresh Control Register Sdrcr Field Descriptions Sdram Refresh Control Register SdrcrSdram Timing Register Sdtimr Field Descriptions Sdram Timing Register SdtimrSdram Timing Register 2 SDTIMR2 Field Descriptions Sdram Timing Register 2 SDTIMR2Peripheral Bus Burst Priority Register Pbbpr Peripheral Bus Burst Priority Register PbbprInterrupt Raw Register IRR Field Descriptions Interrupt Raw Register IRRInterrupt Masked Register IMR Field Descriptions Interrupt Masked Register IMRInterrupt Mask Set Register Imsr Field Descriptions Interrupt Mask Set Register ImsrInterrupt Mask Clear Register Imcr Field Descriptions Interrupt Mask Clear Register ImcrDDR PHY Control Register Ddrphycr Field Descriptions DDR PHY Control Register DdrphycrVTP IO Control Register Vtpiocr Field Descriptions VTP IO Control Register VtpiocrDDR VTP Register Ddrvtpr Field Descriptions DDR VTP Enable Register DdrvtperDDR VTP Enable Register Ddrvtper Field Descriptions DDR VTP Register DdrvtprAdditions/Modifications/Deletions Table A-1. Document Revision HistoryImportant Notice
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