Texas Instruments TMS320C642x DSP DDR2 Sdram Configuration by MRS Command, DDR2 Memory Controller

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Peripheral Architecture

Table 14. DDR2 SDRAM Configuration by MRS Command

DDR2 Memory

 

 

 

 

Controller

 

DDR2 SDRAM

 

 

Address Bus

Value

Register Bit

DDR2 SDRAM Field

Function Selection

DDR_A[12]

0

12

Power Down Exit

Fast exit

DDR_A[11:9]

t_WR

11:9

Write Recovery

Write recovery from autoprecharge. Value of 2,

 

 

 

 

3, 4, 5, or 6 is programmed based on value of

 

 

 

 

the T_WR bit in the SDRAM timing register

 

 

 

 

(SDTIMR).

DDR_A[8]

0

8

DLL Reset

Out of reset

DDR_A[7]

0

7

Mode: Test or Normal

Normal mode

DDR_A[6:4]

CL bit

6:4

CAS Latency

Value of 2, 3, 4, or 5 is programmed based on

 

 

 

 

value of the CL bit in the SDRAM bank

 

 

 

 

configuration register (SDBCR).

DDR_A[3]

0

3

Burst Type

Sequential

DDR_A[2:0]

3h

2:0

Burst Length

8

Table 15. DDR2 SDRAM Configuration by EMRS(1) Command

DDR2 Memory

 

 

 

 

Controller

 

DDR2 SDRAM

 

 

Address Bus

Value

Register Bit

DDR2 SDRAM Field

Function Selection

DDR_A[12]

0

12

Output Buffer Enable

Output buffer enable

DDR_A[11]

0

11

RDQS Enable

RDQS disable

DDR_A[10]

1

10

DQS enable

Disables differential DQS signaling.

DDR_A[9:7]

0

9:7

OCD Calibration Program

Exit OCD calibration

DDR_A[6]

0

6

ODT Value (Rtt)

Cleared to 0 to select 75 ohms. This feature is

 

 

 

 

not supported because the DDR_ODT signal is

 

 

 

 

not pinned out.

DDR_A[5:3]

0

5:3

Additive Latency

0 cycles of additive latency

DDR_A[2]

1

2

ODT Value (Rtt)

Set to 1 to select 75 ohms. This feature is not

 

 

 

 

supported because the DDR_ODT signal is not

 

 

 

 

pinned out.

DDR_A[1]

1

1

Output Driver Impedance

DDR2 drive strength programmed to weak

 

 

 

 

(60%).

DDR_A[0]

0

0

DLL enable

DLL enable

2.13.1Initializing Configuration Registers

Perform the following steps when configuring the DDR2 memory controller memory-mapped registers:

1.Program the DDR PHY control register (DDRPHYCR) by setting the read latency (READLAT) bits to the desired value as well as clearing the DLLPWRDN bit to 0.

2.Program the SDRAM bank configuration register (SDBCR) to the desired value with the TIMUNLOCK bit set to 1 (unlocked).

3.Program the SDRAM timing register (SDTIMR) and SDRAM timing register 2 (SDTIMR2) to the desired values to meet the DDR2 SDRAM memory data sheet specification.

4.Program SDBCR to the desired value with the TIMUNLOCK bit cleared to 0 (locked).

5.Program the RR bit in the SDRAM refresh control register (SDRCR) to the desired value to meet the refresh requirements of the DDR2 SDRAM memory.

32

DDR2 Memory Controller

SPRUEM4A–November 2007

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Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Features Purpose of the PeripheralIndustry Standards Compliance Statement Functional Block DiagramSupported Use Case Statement Clock Control Clock SourceClock Configuration PLLC2 ConfigurationMemory Map 3 DDR2 Memory Controller Internal Clock DomainsSignal Descriptions DDR2 Memory Controller Signal DescriptionsClock enable Active high Pin Type DescriptionDDR2 Sdram Commands Truth Table for DDR2 Sdram CommandsCommand Function Protocol DescriptionsRefresh Mode Refresh CommandDcab Command Deactivation Dcab and DeacDeac Command Actv Command Activation ActvRead Command DDR2 Read CommandWrite WRT Command DDR2 WRT CommandMode Register Set MRS and Emrs DDR2 MRS and Emrs CommandMemory Width and Byte Alignment Addressable Memory RangesEndianness Support Bit External MemoryBit Field Bit Value Bit Description Bank Configuration Register Fields for Address MappingAddress Mapping Logical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram Logical Address-to-DDR2 Sdram Address Map for 16-bit SdramLogical Address-to-DDR2 Sdram Address Map DDR2 Sdram Column, Row, and Bank Access DDR2 Memory Controller Interface DDR2 Memory Controller Fifo DescriptionCommand Ordering and Scheduling, Advanced Concept Command Starvation Possible Race ConditionSelf-Refresh Mode Refresh SchedulingRefresh Urgency Levels Urgency Level DescriptionReset Signal Reset Source Reset ConsiderationsReset Sources VTP IO Buffer Calibration Auto-Initialization SequenceDDR2 Sdram Configuration by MRS Command DDR2 Sdram Configuration by EMRS1 CommandInitializing Configuration Registers DDR2 Memory ControllerPeripheral Architecture DMA Event Support Power ManagementInterrupt Support Emulation Considerations Connecting the DDR2 Memory Controller to DDR2 Memory Supported Use CasesConnecting DDR2 Memory Controller for 32-Bit Connection Configuring Sdram Bank Configuration Register Sdbcr Sdram Bank Configuration Register Sdbcr ConfigurationConfiguring Sdram Refresh Control Register Sdrcr DDR2 Memory Refresh SpecificationConfiguring Sdram Timing Registers Sdtimr and SDTIMR2 Sdram Timing Register Sdtimr ConfigurationSdram Timing Register 2 SDTIMR2 Configuration DDR2 Data Register Field Manual Data Manual FormulaRegister Field Name Description Configuring DDR PHY Control Register DdrphycrDDR PHY Control Register Ddrphycr Configuration Mode D63-32 D31-0Acronym Register Description DDR VTP RegisterBit Field Sdram Status Register SdrstatSdram Status Register Sdrstat Field Descriptions Bit Field Value Description Sdram Bank Configuration Register SdbcrSdram Bank Configuration Register Sdbcr Field Descriptions Reserved Reserved. Always write a 0 to this bit Sdram Refresh Control Register Sdrcr Sdram Refresh Control Register Sdrcr Field DescriptionsSdram Timing Register Sdtimr Sdram Timing Register Sdtimr Field DescriptionsSdram Timing Register 2 SDTIMR2 Sdram Timing Register 2 SDTIMR2 Field DescriptionsPeripheral Bus Burst Priority Register Pbbpr Peripheral Bus Burst Priority Register PbbprInterrupt Raw Register IRR Interrupt Raw Register IRR Field DescriptionsInterrupt Masked Register IMR Interrupt Masked Register IMR Field DescriptionsInterrupt Mask Set Register Imsr Interrupt Mask Set Register Imsr Field DescriptionsInterrupt Mask Clear Register Imcr Interrupt Mask Clear Register Imcr Field DescriptionsDDR PHY Control Register Ddrphycr DDR PHY Control Register Ddrphycr Field DescriptionsVTP IO Control Register Vtpiocr VTP IO Control Register Vtpiocr Field DescriptionsDDR VTP Enable Register Ddrvtper DDR VTP Enable Register Ddrvtper Field DescriptionsDDR VTP Register Ddrvtpr DDR VTP Register Ddrvtpr Field DescriptionsTable A-1. Document Revision History Additions/Modifications/DeletionsImportant Notice
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