Texas Instruments TMS320DM643X DMP Signal Descriptions, Pin Multiplexing, Protocol Description

Page 12

Peripheral Architecture

www.ti.com

2.2Signal Descriptions

The UARTs utilize a minimal number of signal connections to interface with external devices. The UART signal descriptions are included in Table 3. Note that the number of UARTs and their supported features vary on each device, see the device-specific data manual for more details.

 

 

Table 3. UART Signal Descriptions

 

 

 

Signal Name (1)

Signal Type

Function

UTXDn

Output

Serial data transmit

URXDn

Input

Serial data receive

UCTSn

Input

Clear-to-Send handshaking signal

URTSn

Output

Request-to-Send handshaking signal

(1)The value n indicates the applicable UART; that is, UART0, UART1, etc.

2.3Pin Multiplexing

On the DM643x DMP extensive pin multiplexing is used to accommodate the largest number of peripheral functions in the smallest possible package. Pin multiplexing is controlled using a combination of hardware configuration at device reset and software programmable register settings. Refer to the device-specific data manual to determine how pin multiplexing affects the UART.

2.4Protocol Description

2.4.1Transmission

The UART transmitter section includes a transmitter hold register (THR) and a transmitter shift register (TSR). When the UART is in the FIFO mode, THR is a 16-byte FIFO. Transmitter section control is a function of the UART line control register (LCR). Based on the settings chosen in LCR, the UART transmitter sends the following to the receiving device:

•1 START bit

•5, 6, 7, or 8 data bits

•1 PARITY bit (optional)

•1, 1.5, or 2 STOP bits

2.4.2Reception

The UART receiver section includes a receiver shift register (RSR) and a receiver buffer register (RBR). When the UART is in the FIFO mode, RBR is a 16-byte FIFO. Receiver section control is a function of the UART line control register (LCR). Based on the settings chosen in LCR, the UART receiver accepts the following from the transmitting device:

•1 START bit

•5, 6, 7, or 8 data bits

•1 PARITY bit (optional)

•1 STOP bit (any other STOP bits transferred with the above data are not detected)

12

Universal Asynchronous Receiver/Transmitter (UART)

SPRU997C –December 2009

 

 

Submit Documentation Feedback

Copyright © 2009, Texas Instruments Incorporated

Page 11 Page 13
Image 12
Page 11 Page 13
Contents Users Guide Submit Documentation Feedback Revision History Appendix aList of Figures List of Tables Read This First Features Purpose of the PeripheralFunctional Block Diagram Uart Supported Features/Characteristics by InstanceFeature Support Industry Standards Compliance StatementUart Block Diagram FifoClock Generation and Control UartDlhdll BclkBaud Rate Divisor Value Actual Baud Rate Error % Baud Rate Examples for 27 MHz Uart Input ClockStart Parity STOP1 STOP2 Signal Descriptions Pin MultiplexingProtocol Description Endianness Considerations Data FormatParity STOP1 ParityOperation Fifo Modes Character Time for Word LengthsCharacter Time Four Character Times Uart Interface Using Autoflow Diagram Autoflow ControlAutoflow Functional Timing Waveforms for RTS Loopback ControlReset Considerations InitializationInterrupt Support Enable bits Uart Interrupt Requests DescriptionsUart Interrupt Request Interrupt Source CommentPower Management DMA Event SupportEmulation Considerations Changing Operating Mode During Busy Serial Communication Exception ProcessingDivisor Latch Not Programmed Uart RegistersAccess considerations Receiver Buffer Register RBRReceiver Buffer Register RBR Field Descriptions Bit FieldTransmitter Holding Register THR Transmitter Holding Register THR Field DescriptionsBit Field Value Description Interrupt Enable Register IER Interrupt Enable Register IER Field DescriptionsElsi Etbei Erbi ElsiAccess consideration Interrupt Identification Register IIRInterrupt Identification Register IIR Field Descriptions Fifo Control Register FCR Interrupt Identification and Interrupt Clearing InformationIIR Bits Interrupt Type Interrupt SourceFifo Control Register FCR Field Descriptions RxfiftlDMAMODE11 Txclr Rxclr Fifoen DMAMODE1Line Control Register LCR Line Control Register LCR Field DescriptionsDlab EPS PEN STB WLS DlabRelationship Between ST, EPS, and PEN Bits in LCR Number of Stop Bits GeneratedST Bit EPS Bit PEN Bit Parity Option STB BitModem Control Register MCR Modem Control Register MCR Field DescriptionsLoop AFENon-FIFO mode Fifo modeLine Status Register LSR Line Status Register LSR Field DescriptionsSet Elsi = 1 in IER, an interrupt request is generated Divisor Latches DLL and DLH Register RBRDivisor LSB Latch DLL Field Descriptions Divisor MSB Latch DLH Field DescriptionsPeripheral Identification Registers PID1 and PID2 CLS REVCLS TYPPower and Emulation Management Register Pwremumgmt Utrst UrrstFree UtrstDocument Revision History Reference Additions/Modifications/DeletionsImportant Notice
Related manuals
Manual 120 pages 29.22 Kb
Top Page Image Contents